參數(shù)資料
型號(hào)： GS8162Z18BGB-200I
廠商： GSI TECHNOLOGY
元件分類： DRAM
英文描述： 18Mb Pipelined and Flow Through Synchronous NBT SRAM
中文描述： 1M X 18 ZBT SRAM, 6.5 ns, PBGA119
封裝： ROHS COMPLIANT, FPBGA-119
文件頁(yè)數(shù)： 25/34頁(yè)
文件大?。?/td> 788K
代理商： GS8162Z18BGB-200I
Select DR
Capture DR
0
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
1
Select IR
Capture IR
0
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
Test Logic Reset
Run Test Idle
0
1
0
1
1
0
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
GS8162Z18/36B(B/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04a 2/2006
25/34
2004, GSI Technology
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
相關(guān)PDF資料
PDF描述
GS8162Z18BB 18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8162Z18BB-150 18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8162Z18BB-150I 18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8162Z18BB-200 18Mb Pipelined and Flow Through Synchronous NBT SRAM
GS8162Z18BB-200I 18Mb Pipelined and Flow Through Synchronous NBT SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8162Z18BGB-200IV 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 18MBIT 1MX18 6.5NS/3NS 119FBGA - Trays
GS8162Z18BGB-200V 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 18MBIT 1MX18 6.5NS/3NS 119FBGA - Trays
GS8162Z18BGD-200 制造商:GSI Technology 功能描述:SRAM SYNC SGL 2.5V/3.3V 18MBIT 1MX18 6.5NS/3NS 165FBGA - Trays
GS8162Z18BGD-200I 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 6.5NS/3NS 165FBGA - Trays
GS8162Z18BGD-200IV 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 6.5NS/3NS 165FPBGA - Trays
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