參數(shù)資料
      型號(hào): GS8161Z36D-250T
      廠商: Electronic Theatre Controls, Inc.
      元件分類: DRAM
      英文描述: 2048 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70
      中文描述: 35.7流水線和流量,通過同步唑的SRAM
      文件頁數(shù): 1/36頁
      文件大?。?/td> 939K
      代理商: GS8161Z36D-250T
      GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)
      18Mb Pipelined and Flow Through
      Synchronous NBT SRAM
      250 MHz–133 MHz
      2.5 V or 3.3 V V
      DD
      2.5 V or 3.3 V I/O
      100-Pin TQFP
      Commercial Temp
      Industrial Temp
      Rev: 2.15 11/2004
      Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
      1/36
      1998, GSI Technology
      Features
      User-configurable Pipeline and Flow Through mode
      NBT (No Bus Turn Around) functionality allows zero wait
      read-write-read bus utilization
      Fully pin-compatible with both pipelined and flow through
      NtRAM, NoBL and ZBT SRAMs
      IEEE 1149.1 JTAG-compatible Boundary Scan
      2.5 V or 3.3 V +10%/–10% core power supply
      LBO pin for Linear or Interleave Burst mode
      Pin-compatible with 2M, 4M, and 8M devices
      Byte write operation (9-bit Bytes)
      3 chip enable signals for easy depth expansion
      ZZ pin for automatic power-down
      JEDEC-standard 100-lead TQFP and 165-bump FP-BGA
      packages
      Functional Description
      The GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) is an
      18Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like
      ZBT, NtRAM, NoBL or other pipelined read/double late write
      or flow through read/single late write SRAMs, allow
      utilization of all available bus bandwidth by eliminating the
      need to insert deselect cycles when the device is switched from
      read to write cycles.
      Because it is a synchronous device, address, data inputs, and
      read/ write control inputs are captured on the rising edge of the
      input clock. Burst order control (LBO) must be tied to a power
      rail for proper operation. Asynchronous inputs include the
      Sleep mode enable, ZZ and Output Enable. Output Enable can
      be used to override the synchronous control of the output
      drivers and turn the RAM's output drivers off at any time.
      Write cycles are internally self-timed and initiated by the rising
      edge of the clock input. This feature eliminates complex off-
      chip write pulse generation required by asynchronous SRAMs
      and simplifies input signal timing.
      The GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) may
      be configured by the user to operate in Pipeline or Flow
      Through mode. Operating as a pipelined synchronous device,
      in addition to the rising-edge-triggered registers that capture
      input signals, the device incorporates a rising-edge-triggered
      output register. For read cycles, pipelined SRAM output data is
      temporarily stored by the edge triggered output register during
      the access cycle and then released to the output drivers at the
      next rising edge of clock.
      The GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) is
      implemented with GSI's high performance CMOS technology
      and is available in JEDEC-standard 100-pin TQFP and
      165-bump FP-BGA packages.
      Parameter Synopsis
      -250 -225 -200 -166 -150 -133 Unit
      2.5
      4.0
      4.4
      5.0
      6.0
      280
      330
      300
      270
      230
      275
      320
      295
      265
      225
      Pipeline
      3-1-1-1
      t
      KQ
      tCycle
      Curr
      (x18)
      Curr
      (x32/x36)
      Curr
      (x18)
      Curr
      (x32/x36)
      2.7
      3.0
      3.4
      3.8
      6.7
      185
      215
      180
      210
      4.0
      7.5
      165
      190
      165
      185
      ns
      ns
      mA
      mA
      mA
      mA
      3.3 V
      255
      230
      200
      2.5 V
      250
      230
      195
      Flow
      Through
      2-1-1-1
      t
      KQ
      tCycle
      5.5
      5.5
      6.0
      6.0
      6.5
      6.5
      7.0
      7.0
      7.5
      7.5
      8.5
      8.5
      ns
      ns
      3.3 V
      Curr
      (x18)
      Curr
      (x32/x36)
      Curr
      (x18)
      Curr
      (x32/x36)
      175
      200
      175
      200
      165
      190
      165
      190
      160
      180
      160
      180
      150
      170
      150
      170
      145
      165
      145
      165
      135
      150
      135
      150
      mA
      mA
      mA
      mA
      2.5 V
      相關(guān)PDF資料
      PDF描述
      GS8161Z36T-166 2048 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70
      GS8161Z36T-166I 2048 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70
      GS8161Z36T-166IT 4096 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70
      GS8161Z36T-166T 4096 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70
      GS8161Z36T-200 4096 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70
      相關(guān)代理商/技術(shù)參數(shù)
      參數(shù)描述
      GS8161Z36DD-150 制造商:GSI Technology 功能描述:165 BGA - Bulk
      GS8161Z36DD-150I 制造商:GSI Technology 功能描述:165 BGA - Bulk
      GS8161Z36DD-150IV 制造商:GSI Technology 功能描述:165 BGA - Bulk
      GS8161Z36DD-150V 制造商:GSI Technology 功能描述:165 BGA - Bulk
      GS8161Z36DD-200 制造商:GSI Technology 功能描述:165 BGA - Bulk