參數(shù)資料
型號(hào): GS8161Z36BD-250
廠(chǎng)商: GSI TECHNOLOGY
元件分類(lèi): DRAM
英文描述: 18Mb Pipelined and Flow Through Synchronous NBT SRAM
中文描述: 512K X 36 ZBT SRAM, 5.5 ns, PBGA165
封裝: 13 X 15 MM, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù): 23/37頁(yè)
文件大小: 618K
代理商: GS8161Z36BD-250
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
23/37
2004, GSI Technology
Notes:
1.
2.
These parameters are sampled and are not 100% tested.
ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
AC Electrical Characteristics
Parameter
Symbol
-250
-200
-150
Unit
Min
Max
Min
Max
Min
Max
Pipeline
Clock Cycle Time
tKC
4.0
5.0
6.7
ns
Clock to Output Valid
tKQ
2.5
3.0
3.8
ns
Clock to Output Invalid
tKQX
1.5
1.5
1.5
ns
Clock to Output in Low-Z
tLZ
1
1.5
1.5
1.5
ns
Setup time
tS
1.2
1.4
1.5
ns
Hold time
tH
0.2
0.4
0.5
ns
Flow Through
Clock Cycle Time
tKC
5.5
6.5
7.5
ns
Clock to Output Valid
tKQ
5.5
6.5
7.5
ns
Clock to Output Invalid
tKQX
2.0
2.0
2.0
ns
Clock to Output in Low-Z
tLZ
1
2.0
2.0
2.0
ns
Setup time
tS
1.5
1.5
1.5
ns
Hold time
tH
0.5
0.5
0.5
ns
Clock HIGH Time
tKH
1.3
1.3
1.5
ns
Clock LOW Time
tKL
1.5
1.5
1.7
ns
Clock to Output in
High-Z
tHZ
1
1.5
2.5
1.5
3.0
1.5
3.0
ns
G to Output Valid
tOE
2.5
3.0
3.8
ns
G to output in Low-Z
tOLZ
1
0
0
0
ns
G to output in High-Z
tOHZ
1
2.5
3.0
3.8
ns
ZZ setup time
tZZS
2
5
5
5
ns
ZZ hold time
tZZH
2
1
1
1
ns
ZZ recovery
tZZR
20
20
20
ns
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