參數(shù)資料
型號: GS8161Z18BD-150I
廠商: GSI TECHNOLOGY
元件分類: DRAM
英文描述: 18Mb Pipelined and Flow Through Synchronous NBT SRAM
中文描述: 1M X 18 ZBT SRAM, 7.5 ns, PBGA165
封裝: 13 X 15 MM, 1 MM PITCH, FBGA-165
文件頁數(shù): 4/37頁
文件大?。?/td> 618K
代理商: GS8161Z18BD-150I
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
4/37
2004, GSI Technology
100-Pin TQFP Pin Descriptions
Symbol
Type
Description
A
0
, A
1
In
Burst Address Inputs; Preload the burst counter
A
In
Address Inputs
CK
In
Clock Input Signal
B
A
In
Byte Write signal for data inputs DQ
A1
–DQ
A9
; active low
B
B
In
Byte Write signal for data inputs DQ
B1
–DQ
B9
; active low
B
C
In
Byte Write signal for data inputs DQ
C1
–DQ
C9
; active low
B
D
In
Byte Write signal for data inputs DQ
D1
–DQ
D9
; active low
W
In
Write Enable; active low
E
1
In
Chip Enable; active low
E
2
In
Chip Enable—Active High. For self decoded depth expansion
E
3
In
Chip Enable—Active Low. For self decoded depth expansion
G
In
Output Enable; active low
ADV
In
Advance/Load; Burst address counter control pin
CKE
In
Clock Input Buffer Enable; active low
NC
No Connect
DQ
A
I/O
Byte A Data Input and Output pins
DQ
B
I/O
Byte B Data Input and Output pins
DQ
C
I/O
Byte C Data Input and Output pins
DQ
D
I/O
Byte D Data Input and Output pins
ZZ
In
Power down control; active high
FT
In
Pipeline/Flow Through Mode Control; active low
LBO
In
Linear Burst Order; active low.
TMS
Scan Test Mode Select
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