- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383020 > GS816036T-250I (Electronic Theatre Controls, Inc.) Quad 2-input positive-NAND buffers with open collector outputs 14-SO 0 to 70 PDF資料下載
參數(shù)資料
| 型號： | GS816036T-250I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Quad 2-input positive-NAND buffers with open collector outputs 14-SO 0 to 70 |
| 中文描述： | 100萬× 18，512k × 32的，為512k × 36 35.7同步突發(fā)靜態(tài)存儲器 |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 810K |
| 代理商： | GS816036T-250I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
Rev: 2.12 3/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
9/28
1999, Giga Semiconductor, Inc.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
Synchronous Truth Table
Operation
Address
Used
State
Diagram
Key
5
X
X
X
R
R
W
CR
CR
CW
CW
E
1
E
2
ADSP
ADSC
ADV
W
3
DQ
4
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Notes:
1.
X = Don’t Care, H = High, L = Low
2.
E = T (True) if E
2
= 1 and E
3
= 0; E = F (False) if E
2
= 0 or E
3
= 1
3.
W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.
4.
G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown
as “Q” in the Truth Table above).
5.
All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish
basic synchronous or synchronous burst operations and may be avoided for simplicity.
6.
Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See
BOLD
items above.
7.
Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See
ITALIC
items above.
None
None
None
External
External
External
Next
Next
Next
Next
Current
Current
Current
Current
H
L
L
L
L
L
X
H
X
H
X
H
X
H
X
F
F
T
T
T
X
X
X
X
X
X
X
X
X
L
H
L
H
H
H
X
H
X
H
X
H
X
L
X
L
X
L
L
H
H
H
H
H
H
H
H
X
X
X
X
X
X
L
L
L
L
H
H
H
H
X
X
X
X
F
T
F
F
T
T
F
F
T
T
High-Z
High-Z
High-Z
Q
Q
D
Q
Q
D
D
Q
Q
D
D
相關PDF資料 |
PDF描述 |
|---|---|
| GS8160E18 | 16Mb（1M x 18Bit）Sync Burst SRAM(16M位（1M x 18位）同步靜態(tài)RAM(帶2位脈沖地址計數(shù)器)) |
| GS8160E32 | 16Mb（512K x 36Bit）Sync Burst SRAM(16M位（512K x 36位）同步靜態(tài)RAM(帶2位脈沖地址計數(shù)器)) |
| GS8160E36 | 16Mb（256K x 72Bit）Sync Burst SRAM(16M位（256K x 72位）同步靜態(tài)RAM(帶2位脈沖地址計數(shù)器)) |
| GS8160F18 | 16Mb（1M x 18Bit）Sync Burst SRAM(16M位（1M x 18位）同步靜態(tài)RAM(帶2位脈沖地址計數(shù)器)) |
| GS8160F32 | 16Mb（512K x 36Bit）Sync Burst SRAM(16M位（512K x 36位）同步靜態(tài)RAM(帶2位脈沖地址計數(shù)器)) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GS8160E18BGT-150 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 7.5NS/3.8NS 100TQFP - Trays |
| GS8160E18BGT-150I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 7.5NS/3.8NS 100TQFP - Trays |
| GS8160E18BGT-150IV | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 18MBIT 1MX18 7.5NS/3.8NS 100TQFP - Trays |
| GS8160E18BGT-150V | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V/2.5V 18MBIT 1MX18 7.5NS/3.8NS 100TQFP - Trays |
| GS8160E18BGT-200 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V/3.3V 18MBIT 1MX18 6.5NS/3NS 100TQFP - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復。