參數(shù)資料
型號: GS816018T-225I
廠商: Electronic Theatre Controls, Inc.
元件分類: DRAM
英文描述: 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
中文描述: 1M×18,512k×32,512k×36 18M位同步突發(fā)靜態(tài)存儲器
文件頁數(shù): 7/28頁
文件大?。?/td> 810K
代理商: GS816018T-225I
Rev: 2.12 3/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
7/28
1999, Giga Semiconductor, Inc.
Preliminary
GS816018/32/36T-250/225/200/166/150/133
Mode Pin Functions
Note:
There pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
BPR 1999.05.18
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
H
L
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, I
DD
= I
SB
Output Register Control
FT
H or NC
L or NC
Power Down Control
ZZ
H
Note: The burst counter wraps to initial state on the 5th clock.
I
nterleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
相關(guān)PDF資料
PDF描述
GS816036T-166I Quad 2-input positive-NAND buffers with open collector outputs 14-SOIC 0 to 70
GS816036T-200 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS816036T-200I Quad 2-input positive-NAND buffers with open collector outputs 14-PDIP 0 to 70
GS816036T-225 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs
GS816036T-225I Quad 2-input positive-NAND buffers with open collector outputs 14-PDIP 0 to 70
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