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參數(shù)資料
| 型號： | GS8152Z18 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 16Mb Pipelined and Flow Through Synchronous NBT SRAM(16M位流水線式和流通型同步NBT靜態(tài)RAM) |
| 中文描述： | 16Mb的流水線和流量，通過同步唑的SRAM（1,600位流水線式和流通型同步唑靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 16/39頁 |
| 文件大?。?/td> | 757K |
| 代理商： | GS8152Z18 |
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Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
16/39
2000, Giga Semiconductor, Inc.
Preliminary
GS8152Z18/36/72B-225/200/180/166/150/133
reports an error in the cycle following parity check. In x64/x32/x16 mode the device does not drive the 9th data output, even
though the internal ByteSafe parity encoding has been activated. A ByteSafe SRAM, used inx64/ x32/x16 mode, allows parity
protection of data in applications where parity encoding or checking are not otherwise available. As in any system that checks read
parity, reads of un-written memory locations may well produce parity errors. Initialization of the memory should be implemented
to avoid this issue.
In x18/x36/x64 mode this This SRAM includes a write data parity check that checks the validity of data coming into the RAM on
write cycles. In Flow Through mode, write data errors are reported in the cycle following the data input cycle. In Pipeline mode,
write data errors are reported one clock cycle later. (See timing diagram below.) The Data Parity Mode (DP) pin must be tied high
to set the RAM to check for even parity or low to check for odd parity. Read data parity is not checked by the RAM as data validity
is best established at the data’s destination. The Parity Error Output is an open drain output and drives low to indicate a parity error.
Multiple Parity Error Output pins may share a common pull-up resistor.
x16/32/64 Mode (PE = 0) Read Parity Error Output Timing Diagram
CK
Address A
Address B
Address C
Address D
Address E
Address F
D Out A
D Out B
D Out C
D Out D
D Out E
tKQ
tHZ
tKQX
tLZ
DQ
QE
F
P
D Out A
D Out B
D Out C
D Out D
tKQ
tHZ
tKQX
tLZ
DQ
QE
Err A
Err A
Err C
Err C
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