522 - 06 - 02
9
G
The diagram below depicts the active portions of the chip when operating in Receiver mode (Rx/Tx set to logic high level)
with the equalizer, descrambling and NRZI functions all active. In this mode of operation the output of the LOCK pin is logic
high whenever the receiver has successfully locked to the input serial bit stream. The output H is set low after the SAV ID
and is set high after the EAV ID when these sequences are identified in the incoming bit stream.
Note the function available called "Equalizer Control" (EQ). Setting EQ to a logic HIGH level shuts off the equalization
function of the device for implementations where the length of cable to be equalized is very short (less than 10 m).
It is possible to turn off the NRZI and SMPTE Descrambler function by setting SMPTE HIGH. When operating in this mode,
the output of H, will be either "1" or "0" (indeterminate).
Fig. 18 Functional Block Diagram (Receiver Mode)
The diagram below depicts the active portions of the chip when operating in Transmitter mode (Rx/Tx set to logic low level),
with the NRZI and scrambling functions active.
Note that similar to receive mode above, it is possible to turn off the NRZI and SMPTE Scrambler by setting SMPTE high.
RECEIVER OPERATION
EQ
Rx/Tx
SMPTE
GS7000 OPERATING MODE
0
1
0
SMPTE 259M Receiver (Equalizer on, SMPTE / NRZI on)
1
1
0
SMPTE 259M Receiver with equalizer bypassed
0
1
1
Receiver function with NRZI and SMPTE Descrambler disabled, equalizer enabled.
1
1
1
Receiver function with NRZI and SMPTE Descrambler disabled, equalizer bypassed.
TRANSMITTER OPERATION
EQ
Rx/Tx
SMPTE
GS7000 OPERATING MODE
X
0
0
SMPTE 259M Transmitter
X
0
1
Transmitter function with NRZI and SMPTE Scrambler disabled
P to S
S to P
SCRAMBLER
NRZI
ENCODER
DESCRAMBLER
TRS
DETECTOR
NRZI
DECODER
f/10
PLL
MUX
SLICER
EQUALIZER
SIGNAL
LOCK
DETECT
SDO
SDO
SDI
SDI
LOCK
CD
PCLK
IN
EQ
Rx/Tx
D
IN (0,9)
D
OUT(0,9)
PCLK
OUT
H
C
1
C
2
10
10
SMPTE
SMPTE