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參數(shù)資料
| 型號： | GS1545 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | HDTV Serial Digital Equalizing Receiver |
| 中文描述： | 串行數(shù)字高清晰度電視接收機均等 |
| 文件頁數(shù)： | 14/19頁 |
| 文件大?。?/td> | 198K |
| 代理商： | GS1545 |
GENNUM CORPORATION
522 - 28 - 00
14
G
signal is locked to the internal clock, the control output from
the phase detector is refreshed at the transition of each
rising edge of the data input. During this time, the phase of
the clock drifts in one direction.
Fig. 22 Phase Detector Characteristics
During pathological signals, the amount of jitter that the
phase detector will add can be calculated. By choosing the
proper loop bandwidth, the amount of phase detector
induced jitter can also be limited. Typically, for a 1.41MHz
loop bandwidth at 0.2UI input jitter modulation, the phase
detector induced jitter is about 0.015UIp-p. This is not very
significant, even for the pathological signals.
CHARGE PUMP
The charge pump in a slew PLL is different from the charge
pump in a linear PLL. There are two main functions of the
charge pump. One function is to hold the frequency
information of the input data. This information is held by
C
CP1
, which is connected between LFS and LFS. The other
capacitor, C
CP2
between LFS and LFA_GND is used to
remove common mode noise. Both C
CP1
and C
CP2
should
be the same value. The second function of the charge
pump is to provide a binary control voltage to the VCO
depending upon the phase detector output. The output pin,
LFA controls the VCO. Internally there is a 500
pull-up
resistor, which is driven with a 100μA current called
Ι
P
.
Another analog current
Ι
F
, with 5mA maximum drive
proportional to the voltage across the C
CP1,
is applied at the
same
node.
The
voltage
V
LFA_VCC
- 500(
Ι
P
+
Ι
F
) at any time.
at
the
LFA
node
is
Because of the integrator,
Ι
F
changes very slowly whereas
Ι
P
could change at the positive edge of the data transition
as often as a clock period. In the locked position, the
average voltage at the LFA (V
LFA_VCC
–
500(
Ι
P
/2+
Ι
F
) is such
that VCO generates frequency
, equal to the data rate
clock frequency. Since
Ι
P
is changing all the time between
0A and 100μA, there will be two levels generated at the LFA
output.
VCO
The GO1515 is an external hybrid VCO, which has a centre
frequency of 1.485GHz and is also guaranteed to provide
1.485/1.001GHz within the control voltage (3.1V
–
4.65V) of
the GS1545 over process, power supply and temperature.
The GO1515 is a very clean frequency source and,
because of the internal high Q resonator, it is an order of
magnitude more immune to external noise as compared to
on-chip VCOs.
The VCO gain, K
, is nominally 16MHz/V. The control
voltage around the average LFA voltage will be 500 x
Ι
P
/2.
This will produce two frequencies off from the centre by
=K
x 500 x
Ι
P
/2.
LBCONT
The LBCONT pin is used to adjust the loop bandwidth by
externally changing the internal charge pump current. For
maximum loop bandwidth, connect LBCONT to the most
positive power supply. For medium loop bandwidth,
connect LBCONT through a pull-up resistor (R
PULL-UP
). For
low loop bandwidth, leave LBCONT floating. The formula
below shows the loop bandwidth for various configurations.
where LBW nominal is the loop bandwidth when LBCONT is
left floating.
LOOP BANDWIDTH OPTIMIZATION
Since the feed back loop has only digital circuits, the small
signal analysis does not apply to the system. The effective
loop bandwidth scales with the amount of input jitter
modulation index.
PHASE LOCK
The phase lock circuit is used to determine the phase
locked condition. It is done by generating a quadrature
clock by delaying the in-phase clock (the clock whose
falling edge is aligned to the data transition) by 166ps
(0.25UI at 1.5GHz) with the tolerance of 0.05UI. When the
PLL is locked, the falling edge of the in-phase clock is
aligned with the data edges as shown in Figure 23. The
quadrature clock is in a logic high state in the vicinity of
input data transitions. The quadrature clock is sampled and
latched by positive edges of the data transitions. The
generated signal is low pass filtered with an RC network.
The R is an on-chip 20k
resistor and C
PL
is an external
capacitor (recommended value 10nF). The time constant is
about 67μs, or more than a video line.
IN-PHASE CLOCK
INPUT DATA
WITH JITTER
OUTPUT DATA
0.5UI
RE-TIMING
EDGE
PHASE ALIGNMENT
EDGE
LBW
LBW
NOMINAL
25k
5k
(
R
PULL
+
-----------------+
)
UP
–
)
×
=
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