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參數(shù)資料
| 型號(hào)： | GS1545-CQR |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | HDTV Serial Digital Equalizing Receiver |
| 中文描述： | 串行數(shù)字高清晰度電視接收機(jī)均等 |
| 文件頁(yè)數(shù)： | 16/19頁(yè) |
| 文件大小： | 198K |
| 代理商： | GS1545-CQR |
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GENNUM CORPORATION
522 - 28 - 00
16
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the source board with a low frequency oscilloscope
(Bandwidth < 20MHz) that is triggered with an appropriately
filtered DM/DM signal. The true cause of the modulation will
be synchronous and will appear as a stationary signal with
respect to the DM/DM signal.
Figure 25 shows an example of such a situation. An HDTV
SDI signal is modulated with a modulation signal causing
about 0.2UI jitter in Figure 25 (Channel 1). The GS1545
receives this signal and locks to it. Figure 25 (Channel 2)
shows the DM signal. Notice the wave shape of the DM
signal, which is synchronous to the modulating signal. The
DM/DM signal could also be used to compare the output
jitter of the HDTV signal source.
Fig. 25 Jitter Demodulation Signal
LOCK LOGIC
Logic is used to produce the PLL_LOCK signal which is
based on the LFS signal and phase lock signal. When there
is not any data input, the integrator will charge and
eventually saturate at either end. By sensing the saturation
of the integrator, it is determined that no data is present. If
either data is not present or phase lock is low, the lock
signal is made low. Logic signals are used to acquire the
frequency by sweeping the integrator. Injecting a current
into the summing node of the integrator achieves the
sweep. The sweep is disabled once phase lock is asserted.
The direction of the sweep is also changed once LFS
saturates at either end.
BYPASS
The BYPASS block bypasses the reclocked/mute path of
the data whenever a logic low input is applied to the
BYPASS input. In the bypass mode, the mute does not have
any effect on the outputs. Also, the internal PLL still locks to
a valid HDTV signal and shows PLL_LOCK.
SERIAL OUTPUT STAGE
The serial output signals have a nominal voltage of
400mVpp differential, or 200mVpp single ended when
terminated with 50
.
SDO_EN
The SDO_EN enables or disables the serial output driver. To
disable the driver, tie SDO_EN to V
CC
. To enable the driver,
tie SDO_EN to V
EE
. When disabled, the supply current is
reduced by approximately 10mA.
A/D
A/D is a TTL compatible input pin used to select between
the analog or digital input. When A/D is at logic high, the
analog input is selected. When A/D is low, the digital input
is enabled.
CLI
The voltage output of CLI pin is proportional to the amount
of cable present at the GS1545 analog input. With 0m of
cable (800mV input signal levels), the CLI output voltage is
approximately 3.3V. As the cable length increases, the CLI
voltage decreases providing correlation between the CLI
voltage and cable length. CLI voltage will be a function of
the launch voltage and cable type/quality.
MCLADJ
The outputs of the GS1545 can be muted when the input
signal decreases below a preselected input level. The
MCLADJ pin may be left unconnected for applications
where output muting is not required. The use of a Carrier
Detect function with a fixed internal reference does not
solve this problem since the signal to noise ratio on the
circuit board could be significantly less than the default
signal detection level set by the on chip reference.
CARRIER DETECT
The CD pin is a TTL compatible output signal. When a
carrier is detected at the analog input, the CD pin is pulled
low. When a carrier is not detected, the CD will be pulled
high.
SERIAL TO PARALLEL CONVERTER
The high-speed serial to parallel converter accepts
differential clock and data signals from the reclocker core.
The S/P core converts this serial output into a 20-bit wide
data stream (D[19:0]). It also provides a parallel clock,
which is 1/20th the serial clock rate (PCLK_OUT). The
outputs of the S/P block are TTL compatible. When the PLL
loses lock, the parallel clock continues to freewheel. The
parallel clock and data outputs were designed for seamless
interfaces to the GS1500 and GS1510.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS1545-CQRE3 | 制造商:Semtech Corporation 功能描述:High Performance integrated Equalizing Receiver 128-Pin MQFP 制造商:Semtech Corporation 功能描述:HD Equalizing Receiver |
| GS1550MD-EVK2-S2W-WEB | 制造商:GSC 功能描述:GS1550MD Evaluation Kit Includes the GS1550MD-EVB2-S2W-WEB Evaluation Board |
| GS1559 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS1559 HD-LINX-TM II Multi-Rate Deserializer with Loop-Through Cable Driver |
| GS1559_08 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD-LINX II Multi-Rate Deserializer with Loop-Through Cable Driver |
| GS1559-CB | 制造商:Semtech Corporation 功能描述: 制造商:Semtech Corporation 功能描述:HD/SD/ASI Receiver |
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