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參數(shù)資料
| 型號(hào)： | GS1540-CQR |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | HDTV Serial Digital Non-Equalizing Receiver |
| 中文描述： | 高清晰度電視串行數(shù)字非均等接收機(jī) |
| 文件頁數(shù)： | 7/16頁 |
| 文件大小： | 180K |
| 代理商： | GS1540-CQR |
GENNUM CORPORATION
522 - 27- 00
7
G
72
LFA_V
CC
Power
Input
Positive Supply
. Loop filter most positive power supply connection.
73
LFA
Analog
Output
Control Signal Output.
Control voltage for GO1515 VCO.
74
LBCONT
Analog
Input
Control Signal Input
. Used to provide electronic control of Loop
Bandwidth.
75
LFA_V
EE
Power
Input
Negative Supply
. Loop filter most negative power supply connection.
76
DFT_V
EE
Power
Input
Most negative power supply connection - enables the jitter
demodulator functionality. This pin should be connected to ground. If
left floating, the DM function is disabled resulting in a current saving of
340μA.
79, 80
DM, DM
Analog
Output
Test Signal
. Used for manufacturing test only.
These pins must be floating for normal operation.
81, 85
LFS, LFS
Analog
Input
Loop Filter Connections
.
86
IJI
Analog
Output
Status Signal Output
. Approximates the amount of excessive jitter on
the incoming DDI and DDI input.
89
VCO
Analog
Input
Control Signal Input
. Input pin is AC coupled to ground using a 50
transmission line.
91
VCO
Analog
Input
Control Signal Input.
Voltage controlled oscillator input. This pin is
connected to the output pin of the GO1515 VCO.
This pin must be connected to the GO1515 VCO output pin via a 50
transmission line.
93, 96
PLCAP, PLCAP
Analog
Input
Control Signal Input
. Phase lock detect time constant capacitor.
98
PLL_LOCK
TTL
Output
Status Indicator Signal
. This signal is a combination (logical AND) of
the carrier detect and phase lock signals.
When input is present and PLL is locked, the PLL_LOCK goes high
and the outputs are valid. When the PLL_LOCK output is low the data
output is muted (latched at the last state).
PLL_LOCK is independent of the BYPASS signal.
105
BYPASS
TTL
Input
Control Signal Input
. Selectable input that controls whether the input
signal is reclocked or passed through the chip.
When BYPASS is high; the input signal is reclocked.
When BYPASS is low; the input signal is passed through the chip and
not reclocked. Muting does not effect bypassed signal.
106
DDI_V
TT
Analog
Input
Bias Input.
Selectable input for interfacing standard ECL outputs
requiring 50
pull down to V
TT
power supply for a seamless interface.
See Typical Application Circuit for recommended circuit application.
108, 109
DDI, DDI
Differential
ECL/PECL
Input
Digital Data Input Signals.
Digital input signals from a GS1504
Equalizer or HD crosspoint switch.
Because of on chip 50
termination resistors, a PCB trace
characteristic impedance of 50
is recommended.
110
PD_V
CC
Power
Positive Supply
. Phase detector most positive power supply
connection.
112
PDSUB_V
EE
Power
Input
Substrate Connection
. Connect to phase detector
’
s most negative
power supply.
113
PD_V
EE
Power
Input
Negative Supply.
Phase detector most negative power supply
connection.
PIN DESCRIPTIONS (Continued)
NUMBER
SYMBOL
LEVEL
TYPE
DESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS1545 | HDTV Serial Digital Equalizing Receiver |
| GS1545-CQR | HDTV Serial Digital Equalizing Receiver |
| GS1881-IKA | Monolithic Video Sync Separators |
| GS1881-ITA | Monolithic Video Sync Separators |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS1540-CQRE3 | 制造商:Semtech Corporation 功能描述:HD Non-Equalizing Receiver |
| GS1545 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HDTV Serial Digital Equalizing Receiver |
| GS1545_04 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HDTV Serial Digital Equalizing Receiver |
| GS1545-CQR | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS1545-CQRE3 | 制造商:Semtech Corporation 功能描述:High Performance integrated Equalizing Receiver 128-Pin MQFP 制造商:Semtech Corporation 功能描述:HD Equalizing Receiver |
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