- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383014 > GS1522-CQR (Electronic Theatre Controls, Inc.) HDTV Serial Digital Serializer PDF資料下載
參數(shù)資料
| 型號： | GS1522-CQR |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | HDTV Serial Digital Serializer |
| 中文描述： | 高清晰度電視串行數(shù)字串行 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大小： | 414K |
| 代理商： | GS1522-CQR |
GENNUM CORPORATION
522 - 26 - 00
13
G
13. PHASE LOCK
The phase lock circuit is used to determine the phase
locked condition. It is done by generating a quadrature
clock by delaying the in-phase clock (the clock whose
falling edge is aligned to the data transition) by 166ps
(0.25UI at 1.5GHz) with the tolerance of 0.05UI. When the
PLL is locked, the falling edge of the in-phase clock is
aligned with the data edges as shown in Figure 20. The
quadrature clock is in a logic high state in the vicinity of
input data transitions. The quadrature clock is sampled and
latched by positive edges of the data transitions. The
generated signal is low pass filtered with an RC network.
The R is an on-chip 6.67k
resistor and C
PL
is an internal
capacitor (31pF). The time constant is about 200ns.
Fig. 20 PLL Circuit Principles
If the signal is not locked, the data transition phase could
be anywhere with respect to the internal clock or the
quadrature clock. In this case, the normalized filtered
sample of the quadrature clock will be 0.5. When VCO is
locked to the incoming data, data will only sample the
quadrature clock when it is logic high. The normalized
filtered sample quadrature clock will be 1.0. We chose a
threshold of 0.66 to generate the phase lock signal.
Because the threshold is lower than 1, it allows jitter to be
greater than 0.5UI before the phase lock circuit reads it as
“
not phase locked
”
.
14. INPUT JITTER INDICATOR (IJI)
This signal indicates the amount of excessive jitter (beyond
the quadrature clock window 0.5UI), which occurs beyond
the quadrature clock window (see Figure 19) All the input
data transitions occurring outside the quadrature clock
window, will be captured and filtered by the low pass filter
as mentioned in the Phase Lock section. The running time
average of the ratio of the transitions inside the quadrature
clock and outside the quadrature is available at the
PLCAP/PLCAP pins (87 and 85). A signal, IJI, which is the
buffered signal available at the PLCAP is provided so that
loading does not effect the filter circuit. The signal at IJI is
referenced with the power supply such that the factor
V
IJI
/V
CC
is a constant over process and power supply for a
given input jitter modulation. The IJI signal has 10k
output
impedance. Figure 21 shows the relationship of the IJI
signal with respect to the sine wave modulated input jitter.
TABLE 2: Loop Bandwidth Setting Options
RCP1
CCP3
CCP1
CCP2
BW
FACTOR
BW at 0.2 UI JITTER
MODULATION
INDEX
ASYNCHRONOUS
SYNCHRONOUS
A
Open
Open
1.0
1.0
282.9kHz
1.41MHz
60ms
1.25μs
B
50
1.0
5.6
5.6
25.72kHz
129kHz
340ms
11.0μs
IN-PHASE CLOCK
INPUT CLOCK
WITH JITTER
0.8UI
RE-TIMING
EDGE
PHASE ALIGNMENT
EDGE
QUADERATURE
CLOCK
PLCAP SIGNAL
PLCAP SIGNAL
0.25UI
TABLE 3: IJI Voltage as a Function of Sinusoidal Jitter
P-P SINE WAVE JITTER IN UI
IJI VOLTAGE
0.00
4.75
0.15
4.75
0.30
4.75
0.39
4.70
0.45
4.60
0.48
4.50
0.52
4.40
0.55
4.30
0.58
4.20
0.60
4.10
0.63
3.95
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS1540 | HDTV Serial Digital Non-Equalizing Receiver |
| GS1540-CQR | HDTV Serial Digital Non-Equalizing Receiver |
| GS1545 | HDTV Serial Digital Equalizing Receiver |
| GS1545-CQR | HDTV Serial Digital Equalizing Receiver |
| GS1881-IKA | Monolithic Video Sync Separators |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS1522-CQRE3 | 制造商:Gennum Corporation 功能描述:Monolithic Bipolar Integrated Circuit 128-Pin MQFP |
| GS1524 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS1524 HD-LINX-TM II Multi-Rate SDI Adaptive Cable Equalizer |
| GS1524_11 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Multi-Rate SDI Adaptive Cable Equalizer |
| GS1524A | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Adaptive Cable Equalizer |
| GS1524A_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Adaptive Cable Equalizer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。