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參數(shù)資料
| 型號： | GS1510-CQR |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | HDTV Serial Digital Deformatter |
| 中文描述： | 高清晰度電視串行數(shù)字Deformatter |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 106K |
| 代理商： | GS1510-CQR |
GENNUM CORPORATION
522 - 47 - 00
7
G
DETAILED DESCRIPTION
1. DATA INPUT AND OUTPUTS
Data enters and exits the device on the rising edge of
PCLK_IN as shown in Figures 1 and 2. This data can be
scrambled or unscrambled and framed or unframed.
2. DESCRAMBLER AND FRAMER
Both the descrambler and framer can be enabled or
disabled independently of each other to allow the input to
remain scrambled or unscrambled. If the data is
unscrambled, it can be word aligned (framed) or passed
through unaltered.
3. STANDARDS INDICATION
VD_STD[3:0] indicates the standard that the device has
detected. The states of VD_STD[3:0] are shown in the
following standards indication tables.
Note the following in the above tables:
SMPTE260M is 1125 lines/frame
SMPTE274M is 1125 lines/frame
SMPTE295M is 1250 lines/frame
SMPTE296M is 750 lines/frame
See Table 1 for more specific details on the source format
parameters.
67
EAV_ERR
Synchronous
wrt PCLK_IN
Output
Status signal output.
Indicates a TRS error or a mismatch
between the embedded TRS and the flywheel TRS when the
flywheel is enabled. This signal is set high when an error in the
EAV TRS is detected or when the internal flywheel indicates
there is a mismatching EAV TRS. Refer to Fig. 3 for timing
information of EAV_ERR relative to LUMA (DATA_OUT[19:10])
and CHROMA (DATA_OUT [9:0]).
70
TEST
TEST
Test pin.
Used for test purposes only. This pin must be
connected to GND for normal operation.
92, 96, 97, 98,
99,100,101
V
DD
N/A
N/A
Must be connected to V
DD
for normal operation.
95, 102
GND
N/A
N/A
Must be connected to GND for normal operation.
103,104,105, 106,
107, 108, 111, 112,
113, 114, 117, 118,
119,120, 121, 122,
123, 124, 125, 126
DATA_IN [19:0]
Synchronous
wrt PCLK_IN
Input
Input data bus.
DATA_IN [19] is the MSB of the signal (pin 103).
DATA_IN [0] is the LSB of the signal (pin 126).
This data is typically scrambled and not word aligned.
PIN DESCRIPTIONS
NUMBER
SYMBOL
TIMING
TYPE
DESCRIPTION
Interlaced Standards Indication
(VD_STD[3]=1)
VD_STD[3:0]
DESCRIPTION
1000
1080i (30 & 30/1.001Hz
→
D/E) [SMPTE274M]
1001
Reserved
1010
1080i (25Hz
→
F) [SMPTE274M]
1011
Reserved
1100
1080i (25Hz
→
C) [SMPTE295M]
1101
Reserved
1110
1035i (30 & 30/1.001Hz
→
A/B) [SMPTE260M]
1111
Unknown Interlaced with F switching 0/1
Progressive Scan Standards Indication
(VD_STD[3]=0)
VD_STD[3:0]
DESCRIPTION
0000
720p (60 & 60/1.001Hz
→
L/M) [SMPTE296M]
0001
Reserved
0010
1080p (30 & 30/1.001Hz
→
G/H)
[SMPTE274M]
0011
Reserved
0100
1080p (25Hz
→
I) [SMPTE274M]
0101
Reserved
0110
1080p (24 & 24/1.001Hz
→
J/K) [SMPTE274M]
0111
Unknown Progressive with F = 0 always.
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