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參數(shù)資料
| 型號： | GS1500 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | HDTV Serial Digital Deformatter with ANC FIFOs |
| 中文描述： | 高清晰度電視串行數(shù)字Deformatter與FIFO的非洲人國民大會 |
| 文件頁數(shù)： | 7/17頁 |
| 文件大?。?/td> | 146K |
| 代理商： | GS1500 |
GENNUM CORPORATION
522 - 33 - 00
7
G
66
SAV_ERR
Synchronous
wrt PCLK_IN
Output
Status Signal Output.
Indicates a TRS error or a mismatch between
the embedded TRS and the flywheel TRS when the flywheel is
enabled. This signal is set high when an error in the SAV TRS is
detected or when the internal flywheel indicates there is a
mismatching SAV TRS. Refer to Fig. 3 for timing information of
SAV_ERR relative to LUMA (DATA_OUT[19:10]) and CHROMA
(DATA_OUT [9:0]).
67
EAV_ERR
Synchronous
wrt PCLK_IN
Output
Status Signal Output.
Indicates a TRS error or a mismatch between
the embedded TRS and the flywheel TRS when the flywheel is
enabled. This signal is set high when an error in the EAV TRS is
detected or when the internal flywheel indicates there is a
mismatching EAV TRS. Refer to Fig. 3 for timing information of
EAV_ERR relative to LUMA (DATA_OUT[19:10]) and CHROMA
(DATA_OUT [9:0]).
70
TEST
TEST
Test Pin.
Used for test purposes only. This pin must be connected to
GND for normal operation.
71
YCS_ERR
Synchronous
wrt PCLK_IN
Output
Status Signal Output.
Indicates a checksum error or a mismatch
between the embedded checksum and the calculated checksum
for the LUMA (DATA_OUT[19:10]) channel. When YCS_ERR is high,
an error in the checksum is detected. Refer to Fig. 18 for timing
information of YCS_ERR relative to LUMA (DATA_OUT[19:10]).
72
CCS_ERR
Synchronous
wrt PCLK_IN
Output
Status Signal Output.
Indicates a checksum error or a mismatch
between the embedded checksum and the calculated checksum
for the CHROMA (DATA_OUT[9:0]) channel. When CCS_ERR is
high, an error in the checksum is detected. Refer to Fig. 18 for
timing information of CCS_ERR relative to CHROMA (DATA_OUT
[9:0]).
73, 74, 75
FF_STA[2:0]
Output
Control Signal Output.
FF_STA[2:0] is the FIFO status output to
indicate the content level of the internal FIFOs.
FF_STA[2:0]=000: Error flag, FIFO is under run .
FF_STA[2:0]=001: FIFO is empty.
FF_STA[2:0]=010: FIFO is almost empty; 32 bytes filled
FF_STA[2:0]=011: FIFO is ready.
FF_STA[2:0]=100: FIFO is half full.
FF_STA[2:0]=101: FIFO is almost full; 992 bytes filled
FF_STA[2:0]=110: FIFO is full.
FF_STA[2:0]=111: Error flag, FIFO is over run.
When ANC_Y/C is high, FF_STA[2:0] indicates the status of the
LUMA ANC data FIFO. When ANC_Y/C is low, FF_STA[2:0]
indicates the status of the CHROMA ANC data FIFO. See Fig. 6 to
Fig. 15 for timing information.
76, 77, 80, 83,
84, 85, 86, 87,
88, 89
ANC_OUT[9:0]
Synchronous
wrt PCLK_IN
Output
ANC Data Output Bus.
ANC_OUT[9] is the MSB and ANC_OUT[0] is
the LSB. When ANC_Y/C is high, ANC_OUT[9:0] presents ANC data
from the LUMA FIFO. When ANC_Y/C is low, ANC_OUT[9:0]
presents ANC data from the CHROMA FIFO.
92
R_CLK
N/A
Input
Input Clock Signal.
Used to read information from the internal
FIFO(s). On the rising edge of R_CLK, the device will extract the
next word from the internal LUMA/CHROMA channel data FIFO,
depending on the status of the ANC_Y/C signal.
95
FOEN
Non-
synchronous
Input
Control Signal Input.
Used to enable or disable the internal FIFO
outputs. When FOEN is low, the FIFO ANC_OUT[9:0] and
FF_STA[2:0] are enabled. When FOEN is high, the FIFO
ANC_OUT[9:0] and FF_STA[2:0] outputs are in a high Z state. Note
that the internal read address pointers are updated independently
of FOEN.
PIN DESCRIPTIONS (Continued)
NUMBER
SYMBOL
TIMING
TYPE
DESCRIPTION
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