- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄383013 > GS1500-CQR (Electronic Theatre Controls, Inc.) HDTV Serial Digital Deformatter with ANC FIFOs PDF資料下載
參數(shù)資料
| 型號(hào)： | GS1500-CQR |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | HDTV Serial Digital Deformatter with ANC FIFOs |
| 中文描述： | 高清晰度電視串行數(shù)字Deformatter與FIFO的非洲人國(guó)民大會(huì) |
| 文件頁(yè)數(shù)： | 6/17頁(yè) |
| 文件大小： | 146K |
| 代理商： | GS1500-CQR |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)當(dāng)前第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)
GENNUM CORPORATION
522 - 33 - 00
6
G
27
ANC_DATA_C
Synchronous
wrt PCLK_IN
Output
Control Signal Output.
This signal indicates the position of the
embedded ANC data in the outgoing CHROMA (DATA_OUT[9:0])
data stream. ANC_DATA_C goes high for the entire time that an
ANC_DATA packet is present in the CHROMA (DATA_OUT[9:0])
data stream whether it be in the active video area or the HANC
area. Refer to Fig. 17 for timing of ANC_DATA_C relative to
CHROMA (DATA_OUT[9:0]). During detection of ANC data, any
errors in the data count (DC) packet will consequently cause errors
in the duration of the flags. Bit errors in an ANC header will prevent
the packet from being detected.
28, 29, 30, 31
VD_STD[3:0]
Synchronous
wrt PCLK_IN
Output
Control Signal Output.
VD_STD[3:0] indicates which input video
standard the device has detected. The GS1500 will indicate all of
the formats in SMPTE292M (see Table 3) plus it will indicate an
unknown interlace or progressive scan format.
32
LINE_CRC_ERR_C
Synchronous
wrt PCLK_IN
Output
Status Signal Output.
Indicates a difference in the calculated versus
embedded CRC in the CHROMA channel. When LINE_CRC_ERR_C
is high, it indicates that the GS1500 has detected a difference
between the line based CRCs it calculates for the CHROMA
channel and the line based CRCs embedded within the CHROMA
channel. When LINE_CRC_ERR_C is low, the embedded and
calculated CRC's match. Refer to Fig. 19 for timing information of
LINE_CRC_ERR_C.
33
LINE_CRC_ERR_Y
Synchronous
wrt PCLK_IN
Output
Status Signal Output.
Indicates a difference in the calculated versus
embedded CRC in the LUMA channel. When LINE_CRC_ERR_Y is
high, it indicates that the GS1500 has detected a difference
between the line based CRCs it calculates for the LUMA channel
and the line based CRCs embedded within the LUMA channel.
When LINE_CRC_ERR_Y is low, the embedded and calculated
CRC's match. Refer to Fig. 19 for timing information of
LINE_CRC_ERR_Y.
34
FIFO_L
Synchronous
wrt PCLK_IN
Output
Control Signal Output.
Used to control an external FIFO(s). FIFO_L
is normally high, but is set low for the EAV or SAV word depending
on the state of F_E/S. Refer to Fig. 4 for timing information of FIFO_L
relative to LUMA (DATA_OUT[19:10]) and CHROMA
(DATA_OUT[9:0]).
35
TN
TEST
Test Pin.
Used for test purposes only. This pin must be connected to
V
DD
for normal operation
36
OEN
Non-
synchronous
Input
Control Signal Input.
Used to enable the DATA_OUT[19:0] output
bus or set it in a high Z state. When OEN is low, the LUMA
(DATA_OUT[19:10]) and CHROMA (DATA_OUT [9:0]) busses are
enabled. When OEN is high, these busses are in a high Z state.
39, 40, 41, 42,
43, 44, 45, 48,
49, 52
DATA_OUT[9:0]
(CHROMA
channel)
Synchronous
wrt PCLK_IN
Output
CHROMA Output Data Bus.
DATA_OUT [9] is CHROMA_OUT[9]
which is the MSB of the CHROMA output signal (pin 52). DATA_OUT
[0] is CHROMA_OUT[0] which is the LSB of the CHROMA output
signal (pin 39).
53, 54, 55, 56,
57, 60, 61, 62,
63, 64
DATA_OUT[19:10]
(LUMA channel)
Synchronous
wrt PCLK_IN
Output
LUMA Output Data Bus.
DATA_OUT [19] is LUMA_OUT[9] which is
the MSB of the LUMA output signal. (pin 64) DATA_OUT [10] is
LUMA_OUT[0] which is the LSB of the LUMA output signal (pin 53).
65
LN_ERR
Synchronous
wrt PCLK_IN
Output
Status Signal Output.
Used to indicate a Line Number error or a
mismatch between the embedded line number and the flywheel line
number when the flywheel is enabled. When LN_ERR is high, a line
number error is detected or the internal flywheel indicates
mismatching line numbers. Refer to Fig. 3 for timing information of
LN_ERR relative to LUMA (DATA_OUT[19:10]) and CHROMA
(DATA_OUT [9:0]) Since LN_ERR depends on the sequence of line
numbers, a line number error will actually cause LN_ERR to go high
for two lines.
PIN DESCRIPTIONS (Continued)
NUMBER
SYMBOL
TIMING
TYPE
DESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS1504 | HDTV Adaptive Equalizer |
| GS1504-CKD | HDTV Adaptive Equalizer |
| GS1504-CTD | HDTV Adaptive Equalizer |
| GS1508 | HDTV Cable Driver |
| GS1508-CKA | HDTV Cable Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS1500M | 制造商:GainSpan Corporation 功能描述:WIFI MODULE 802.11B INT PA JTAG |
| GS1500M22 | 制造商:GAINSPAN CORPORATION 功能描述:802.11 WI-FI MODULE 制造商:GAINSPAN CORPORATION 功能描述:48 pins low power WiFi module with Internal PA, PCB Trace Antenna and External 制造商:GSC 功能描述:48 pins low power WiFi module with Internal PA, PCB Trace Antenna and External |
| GS1500M22-100 | 功能描述:RF TXRX MODULE WIFI TRACE + U.FL 制造商:gainspan corporation 系列:- 包裝:托盤(pán) 零件狀態(tài):有效 射頻系列/標(biāo)準(zhǔn):WiFi 協(xié)議:802.11b/g/n 調(diào)制:- 頻率:2.4GHz 數(shù)據(jù)速率:54Mbps 功率 - 輸出:14dBm 靈敏度:- 串行接口:I2C，JTAG，SPI，UART 天線(xiàn)類(lèi)型:集成式，跟蹤 + U.FL 存儲(chǔ)容量:- 電壓 - 電源:3.3V 電流 - 接收:- 電流 - 傳輸:- 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:模塊 標(biāo)準(zhǔn)包裝:100 |
| GS1500M22-50 | 制造商:GAINSPAN CORPORATION 功能描述:802.11 WI-FI MODULE |
| GS1500M-EVB2-S2W-WEB-R2 | 制造商:GAINSPAN CORPORATION 功能描述:EVAL BOARD 802.11 制造商:GAINSPAN CORPORATION 功能描述:GS1500M Evaluation Board Includes the GS1500M22 Module |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。