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參數(shù)資料
| 型號(hào)： | GP2015 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | GPS Receiver RF Front End(用于全球定位系統(tǒng)（GPS）接收器的第二代RF前端) |
| 中文描述： | GPS接收機(jī)射頻前端（用于全球定位系統(tǒng)（GPS）的接收器的第二代射頻前端） |
| 文件頁(yè)數(shù)： | 22/24頁(yè) |
| 文件大?。?/td> | 154K |
| 代理商： | GP2015 |
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GP2015
7
Pin No.
Signal Name
Input/Output
Description
18
VDD (IO)
Input
Positive supply to the Digital Interface. (See Note 2)
19
PDn
Input
Power-Down control input.
A TTL compatible input, which when set to logic high, will
disable ALL of the GP2015 functions, except the power-on
reset block. Useful to reduce the total power consumption of
the GP2015. If this feature is not required, the pin should be
connected to 0V (VEE/GND).
20
TEST
Input
Test control input - Disable PLL.
A TTL compatible input, which when set to logic high, will
disable the on-chip PLL, by disconnecting the divided-down
VCO signal to the phase-detector. The VCO will free run at its
upper range of frequency operation. If this feature is not
required, the pin should be connected to 0V (VEE/GND).
21
LD
Output
PLL Lock Detect output.
A TTL compatible output, which indicates if the PLL is phase-
locked to the PLL reference oscillator. Will become logic high
only when phase-lock is achieved.
22
VEE (DIG)
Input
Negative supply to the PLL and A to D converter.
23
AGC-
Output
AGC Capacitor output - inverse phase.
One side of a balanced output from the AGC block within IF
Stage 3, to which an external capacitor is connected to set the
AGC time-constant.
24
AGC+
Output
AGC Capacitor output - true phase.
One side of a balanced output from the AGC block within IF
Stage 3, to which an external capacitor is connected to set the
AGC time-constant.
25
N/C
Not connected. (See Note 4)
26
VCC (DIG)
Input
Positive supply to the PLL and A to D converter.
27
REF 2
Input
10.000MHz PLL Reference signal input .
Input to which an externally generated 10.000MHz PLL
reference signal should be ac coupled, if an external PLL
reference frequency source (e.g TCXO) is used (see fig. 6).
If no external reference is used, this pin forms part of the on-
chip PLL reference oscillator, in conjunction with an external
10.000MHz crystal (see fig. 5).
28
REF 1
Input
PLL reference oscillator auxillary connection.
Used in conjunction with Pin 27 (REF 2) to allow a 10.000MHz
external crystal to provide the PLL reference signal if no
external PLL reference frequency source (e.g TCXO) is used.
This pin should NOT be connected if an external TCXO is
being used (see fig. 5).
29, 35
VCC (RF)
Input
Positive supply to the RF input and Stage 1 IF mixer.
Both pins are connected internally, but must both be connected
to VCC externally, to keep series inductance to a minimum.
30, 31,
VEE (RF)
Input
Negative supply to the RF input and Stage 1 IF mixer. The
33, 34
pins are all connected internally, but must ALL be connected
to 0V (VEE/GND) externally, to keep series inductance to a
minimum.
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