參數(shù)資料
型號(hào)： GMS97L52
廠商： HYNIX SEMICONDUCTOR INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁(yè)數(shù)： 9/39頁(yè)
文件大?。?/td> 254K
代理商： GMS97L52
8-Bit CMOS Microcontorller
GMS97C2051/L2051
HYUNDAI MicroElectonics
9
Table 7
. Interrupt Sources and their corresponding Interrupt Vectors
Interrupt
Source
Vector Address
External interrupt 0
Timer0
External Interrupt 1
Timer1
Serial Port Interrupt
System Reset
IE0
TF0
IE1
TF1
RI + TI
RST
0003H
000BH
0013H
001BH
0023H
0000H
Table 8
. Interrupt Priority-Within-Level
Interrupt Source
Priority
External interrupt 0
Timer0 interrupt
External Interrupt 1
Timer1 interrupt
Serial Port Interrupt
IE0
TF0
IE1
TF1
RI + TI
Highest
Lowest
Restrictions on Certain Instructions
The GMS97C2051/L2051 is an economical and cost-
effective member of HYUNDAI MicroElectronics
growing family of microcontrollers. It contains
2Kbytes of EPROM program memory. It is fully
compatible with the MCS-51 architecture, and can be
programmed using the MCS-51 instruction set. How-
ever, there are a few considerations one must keep in
mind when utilizing certain instructions to program this
device.
1. Branching instructions:
LCALL, LJMP, ACALL, AJMP, SJMP, JMP
@A+DPTR
These unconditional branching instructions will ex-
ecute correctly as long as the programmer keeps in
mind that the destination branching address must fall
within the physical boundaries of the program memory
size
(locations
00H
GMS97C2051/L2051). Violating the physical space
limits may cause unknown program behavior.
CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ
With these conditional branching instructions the same
to
7FFH
for
the
rule above applies. Again, violating the memory
boundaries may cause erratic execution.
For applications involving interrupts the normal inter-
rupt service routine address locations of the 80C51
family architecture have been preserved.
2. MOVX-related instructions, Data Memory:
The GMS97C2051/L2051 contains 128 bytes of inter-
nal data memory. Thus, in the GMS97C2051/L2051
the stack depth is limited to 128 bytes, the amount of
available RAM. External DATA memory access is
not supported in this device, nor is external PRO-
GRAM memory execution. Therefore, no MOVX [...]
instructions should be included in the program.
A typical 80C51 assembler will still assemble instruc-
tions, even if they are written in violation of the restric-
tions mentioned above. It is the responsibility of the
controller user to know the physical features and limi-
tations of the device being used and adjust the instruc-
tions used correspondingly.
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