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參數(shù)資料
| 型號： | GMS81C7216LQ |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 48/93頁 |
| 文件大?。?/td> | 853K |
| 代理商： | GMS81C7216LQ |
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GMS81C1404/GMS81C1408
46
June. 2001 Ver 1.2
timer register T0 (T1) increases and matches TDR0
(TDR1).
This timer interrupt in capture mode is very useful when
the pulse width of captured signal is more wider than the
maximum period of Timer.
For example, in Figure 13-8 , the pulse width of captured
signal is wider than the timer data value (FF
H
) over 2
times. When external interrupt is occurred, the captured
value (13
H
) is more little than wanted value. It can be ob-
tained correct value by counting the number of timer over-
flow occurrence.
Timer/Counter still does the above, but with the added fea-
ture that a edge transition at external input INTx pin causes
the current value in the Timer x register (T0,T1), to be cap-
tured into registers CDRx (CDR0, CDR1), respectively.
After captured, Timer x register is cleared and restarts by
hardware.
It has three transition modes: “falling edge”, “rising edge”,
“both edge” which are selected by interrupt edge selection
register IEDS (Refer to External interrupt section). In ad-
dition, the transition at INTx pin generate an interrupt.
Note:
The CDRx, TDRx and Tx are in same address. In
the capture mode, reading operation is read the
CDRx, not Tx because path is opened to the CDRx,
and TDRx is only for writing operation.
Figure 13-6 8-bit Capture Mode
÷
1
÷
2
÷
8
TM0
ADDRESS : D0H
RESET VALUE : --000000
-
-
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
TM1
ADDRESS : D2H
RESET VALUE : 00000000
POL
16BIT
PWME
CAP1
T1CK1
T1CK0
T1CN
T1ST
-
-
1
X
X
X
X
X
X
0
0
1
X
X
X
X
÷
2
÷
4
÷
8
÷
32
÷
128
÷
512
÷
2048
fxin
EC0
Edge Detector
MUX
MUX
1
1
T0 (8-bit)
CDR0 (8-bit)
T0IF
CLEAR
COMPARATOR
TIMER 0
INTERRUPT
T0ST
0 : Stop
1 : Clear and Start
T0CN
T1CN
T0CK[2:0]
T1CK[1:0]
TDR0 (8-bit)
INT0IF
INT 0
INTERRUPT
INT0
T1 (8-bit)
CDR1 (8-bit)
T1IF
CLEAR
COMPARATOR
TIMER 1
INTERRUPT
TDR1 (8-bit)
INT1IF
INT 1
INTERRUPT
INT1
T0ST
0 : Stop
1 : Clear and Start
IEDS[1:0]
IEDS[3:2]
CAPTURE
CAPTURE
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