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參數資料
| 型號： | GMS81C5016 |
| 廠商： | Hynix Semiconductor Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT SINGLE CHIP MICROCONTROLLERS |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數： | 50/93頁 |
| 文件大?。?/td> | 853K |
| 代理商： | GMS81C5016 |
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GMS81C1404/GMS81C1408
48
June. 2001 Ver 1.2
13.5 16-bit Capture Mode
16-bit capture mode is the same as 8-bit capture, except
that the Timer register is being run will 16 bits.
The clock source of the Timer 0 is selected either internal
or external clock by bit T0CK2, T0CK1 and T0CK0.
In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1
should be set to “1” respectively.
Figure 13-9 16-bit Capture Mode
13.6 PWM Mode
The GMS81C1404 and GMS81C1408 has a two high
speed PWM (Pulse Width Modulation) functions which
shared with Timer1 (Timer 3). In this document, it will be
explained only PWM0.
In PWM mode, pin RB4/COMP0/PWM0 outputs up to a
10-bit resolution PWM output. This pin should be config-
ure as a PWM output by setting “1” bit PWM0O in RB-
FUNC register. (PWM1 output by setting “1” bit PWM1O
in RBFUNC)
The period of the PWM output is determined by the
T1PPR (PWM0 Period Register) and PWM0HR[3:2]
(bit3,2 of PWM0 High Register) and the duty of the PWM
output is determined by the T1PDR (PWM0 Duty Regis-
ter) and PWM0HR[1:0] (bit1,0 of PWM0 High Register).
The user writes the lower 8-bit period value to the T1PPR
and the higher 2-bit period value to the PWM0HR[3:2].
And writes duty value to the T1PDR and the
PWM0HR[1:0] same way.
The T1PDR is configure as a double buffering for glitch-
less PWM output. In Figure 13-10 , the duty data is trans-
ferred from the master to the slave when the period data
matched to the counted value. (i.e. at the beginning of next
duty cycle)
PWM Period = [PWM0HR[3:2]T1PPR] X Source Clock
PWM Duty = [PWM0HR[1:0]T1PDR] X Source Clock
The relation of frequency and resolution is in inverse pro-
portion. Table 13-2 shows the relation of PWM frequency
vs. resolution.
TM0
ADDRESS : D0H
RESET VALUE : --000000
-
-
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
TM1
ADDRESS : D2H
RESET VALUE : 00000000
POL
16BIT
PWME
CAP1
T1CK1
T1CK0
T1CN
T1ST
-
-
1
X
X
X
X
X
X
1
0
X
1
1
X
X
÷
2
÷
4
÷
8
÷
32
÷
128
÷
512
÷
2048
fxin
EC0
Edge Detector
MUX
1
T0 + T1 (16-bit)
TDR1
(8-bit)
T0IF
CLEAR
COMPARATOR
TIMER 0
INTERRUPT
T0ST
0 : Stop
1 : Clear and Start
T0CN
T0CK[2:0]
TDR0
(8-bit)
INT0IF
INT 0
INTERRUPT
INT0
IEDS[1:0]
CAPTURE
CDR1
(8-bit)
CDR0
(8-bit)
X: The value “0” or “1” corresponding your operation.
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