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| 型號： | GMS81C5016-XXXDT |
| 英文描述： | MICROCONTROLLER|8-BIT|CMOS|SOP|28PIN|PLASTIC |
| 中文描述： | 單片機| 8位|的CMOS |專科| 28腳|塑料 |
| 文件頁數(shù)： | 44/93頁 |
| 文件大?。?/td> | 853K |
| 代理商： | GMS81C5016-XXXDT |
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GMS81C1404/GMS81C1408
42
June. 2001 Ver 1.2
13. TIMER / COUNTER
The GMS81C1404 and GMS81C1408 has four Timer/
Counter registers. Each module can generate an interrupt
to indicate that an event has occurred (i.e. timer match).
Timer 0 and Timer 1 can be used either the two 8-bit Tim-
er/Counter or one 16-bit Timer/Counter by combining
them. Also Timer 2 and Timer 3 are same. In this docu-
ment, explain Timer 0 and Timer 1 because Timer2 and
Timer3 same with Timer 0 and Timer 1.
In the “timer” function, the register is increased every in-
ternal clock input. Thus, one can think of it as counting in-
ternal clock input. Since a least clock consists of 2 and
most clock consists of 2048 oscillator periods, the count
rate is 1/2 to 1/2048 of the oscillator frequency in Timer0.
And Timer1 can use the same clock source too. In addition,
Timer1 has more fast clock source (1/1 to 1/8).
In the “counter” function, the register is increased in re-
sponse to a 0-to-1 (rising edge) transition at its correspond-
ing external input pin, EC0(Timer 0) or EC1(Timer 2).
Note:
In the external event counter function, the RA0/EC0
pin has not a schmitt trigger, but a normal input port.
Therefore, it may be count more than input event
signal if the noise interfere in slow transition input
signal .
In addition the “capture” function, the register is increased
in response external interrupt same with timer function.
When external interrupt edge input, the count register is
captured into capture data register CDRx.
Timer1 and Timer 3 are shared with “PWM” function and
“Compare output” function
It has seven operating modes: “8-bit timer/counter”, “16-
bit timer/counter”, “8-bit capture”, “16-bit capture”, “8-bit
compare output”, “16-bit compare output” and “10-bit
PWM” which are selected by bit in Timer mode register
TMx as shown in Figure 13-1 and Table 13-1 .
Figure 13-1 Timer Mode Register (TMx, x = 0~3)
Timer 0(2) Mode Register
TM0(2)
ADDRESS : D0H (D6H for TM2)
RESET VALUE : --000000
-
-
CAPx
TxCK2
TxCK1
TxCK0
TxCN
TxST
Timer 1(3) Mode Register
TM1(3)
ADDRESS : D2H (D8H for TM3)
RESET VALUE : 00000000
POL
16BIT
PWMxE
CAPx
TxCK1
TxCK0
TxCN
TxST
CAP0
CAP2
Capture mode selection bit.
0 : Disables Capture
1 : Enables Capture
T0CN
T2CN
Continue control bit
0 : Stop counting
1 : Start counting continuously
T0CK[2:0]
T2CK[2:0]
Input clock selection
000 : fxin
÷
2, 100 : fxin
÷
128
001 : fxin
÷
4, 101 : fxin
÷
512
010 : fxin
÷
8, 110 : fxin
÷
2048
011 : fxin
÷
32, 111 : External Event ( EC0(1) )
T0ST
T2ST
Start control bit
0 : Stop counting
1 : Counter register is cleared and start again
POL
PWM Output Polarity
0 : Duty active low
1 : Duty active high
T1CK[2:0]
T3CK[2:0]
Input clock selection
00 : fxin 10 : fxin
÷
8
01 : fxin
÷
2 11 : using the Timer 0 clock
16BIT
16-bit mode selection
0 : 8-bit mode
1 : 16-bit mode
T1CN
T3CN
Continue control bit
0 : Stop counting
1 : Start counting continuously
PWM0E
PWM1E
PWM enable bit
0 : Disables PWM
1 : Enables PWM
T1ST
T3ST
Start control bit
0 : Stop counting
1 : Counter register is cleared and start again
CAP1
CAP3
Capture mode selection bit.
0 : Disables Capture
1 : Enables Capture
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