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GMS81C1404/GMS81C1408
June. 2001 Ver 1.2
29
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C0H
RA
RA Port Data Register
C1H
RAIO
RA Port Direction Register
C2H
RB
RB Port Data Register
C3H
RBIO
RB Port Direction Register
C4H
RC
RC Port Data Register
C5H
RCIO
RC Port Direction Register
C6H
RD
RD Port Data Register
C7H
RDIO
RD Port Direction Register
CAH
RAFUNC
ANSEL7
ANSEL6
ANSEL5
ANSEL4
ANSEL3
ANSEL2
ANSEL1
ANSEL0
CBH
RBFUNC
TMR2OV
EC1I
PWM1O
PWM0O
INT1I
INT0I
BUZO
AVREFS
CCH
PUPSEL
-
-
-
-
PUPSEL3 PUPSEL2 PUPSEL1 PUPSEL0
CDH
RDFUNC
-
-
-
-
-
-
INT3I
INT2I
D0H
TM0
-
-
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
D1H
T0/TDR0/
CDR0
Timer0 Register / Timer0 Data Register / Capture0 Data Register
D2H
TM1
POL
16BIT
PWM0E
CAP1
T1CK1
T1CK0
T1CN
T1ST
D3H
TDR1/
T1PPR
Timer1 Data Register / PWM0 Period Register
D4H
T1/CDR1/
T1PDR
Timer1 Register / Capture1 Data Register / PWM0 Duty Register
D5H
PWM0HR
PWM0 High Register
D6H
TM2
-
-
CAP2
T2CK2
T2CK1
T2CK0
T2CN
T2ST
D7H
T2/TDR2/
CDR2
Timer2 Register / Timer2 Data Register / Capture2 Data Register
D8H
TM3
POL
16BIT
PWM1E
CAP3
T3CK1
T3CK0
T3CN
T3ST
D9H
TDR3/
T3PPR
Timer3 Data Register / PWM1 Period Register
DAH
T3/CDR3/
T3PDR
Timer3 Register / Capture3 Data Register / PWM1Duty Register
DBH
PWM1HR
PWM1 High Register
DEH
BUR
BUCK1
BUCK0
BUR5
BUR4
BUR3
BUR2
BUR1
BUR0
E0H
SIOM
POL
SRDY
SM1
SM0
SCK1
SCK0
SIOST
SIOSF
E1H
SIOR
SPI DATA REGISTER
E2H
IENH
INT0E
INT1E
T0E
T1E
INT2E
INT3E
T2E
T3E
E3H
IENL
ADE
WDTE
BITE
SPIE
-
-
-
-
E4H
IRQH
INT0IF
INT1IF
T0IF
T1IF
INT2IF
INT3IF
T2IF
T3IF
E5H
IRQL
ADIF
WDTIF
BITIF
SPIF
-
-
-
-
E6H
IEDS
IED3H
IED3L
IED2H
IED2L
IED1H
IED1L
IED0H
IED0L
Table 9-3 Control Registers of GMS81C1404 and GMS81C1408
These registers of shaded area can not be accessed by bit manipulation instruction as “SET1, CLR1”, but should be accessed by
register operation instruction as “LDM dp,#imm”.
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