參數(shù)資料
型號： GMS81C2012
廠商： Hynix Semiconductor Inc.
英文描述： HYUNDAI MICRO ELECTRONICS 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 現(xiàn)代微電子8位單晶片微控制器
文件頁數(shù)： 69/93頁
文件大?。?/td> 853K
代理商： GMS81C2012
GMS81C1404/GMS81C1408
June. 2001 Ver 1.2
67
Figure 19-3 Timing of STOP Mode Release by RESET
19.2 STOP Mode using Internal RCWDT
In the STOP mode using Internal RC-Oscillated Watchdog
Timer, the on-chip oscillator is stopped. But internal RC
oscillation circuit is oscillated in this mode. The on-chip
RAM and Control registers are held. The port pins out the
values held by their respective port data register, port di-
rection registers.
The Internal RC-Oscillated Watchdog Timer mode is
activated by execution of STOP instruction after set-
ting the bit RCWDT of CKCTLR to “1”. ( This register
should be written by byte operation. If this register is
set by bit manipulation instruction, for example “set1”
or “clr1” instruction, it may be undesired operation )
Note:
After STOP instruction, at least two or more NOP in-
struction should be written
Ex)
LDM WDTR
,#1111_1111B
LDM CKCTLR
,#00
1
0_1110B
STOP
NOP
NOP
Release the STOP mode using internal RCWDT
The exit from STOP mode using Internal RC-Oscillated
Watchdog Timer is hardware reset or external interrupt.
Reset re-defines all the Control registers but does not
change the on-chip RAM. External interrupts allow both
on-chip RAM and Control registers to retain their values.
If I-flag = 1, the normal interrupt response takes place. In
this case, if the bit WDTON of CKCTLR is set to “0” and
the bit WDTE of IENH is set to “1”, the device will exe-
cute the watchdog timer interrupt service routine.(Figure
19-4 ) However, if the bit WDTON of CKCTLR is set to
“1”, the device will generate the internal RESET signal
and execute the reset processing. (Figure 19-5 )
If I-flag = 0, the chip will resume execution starting with
the instruction following the STOP instruction. It will not
vector to interrupt service routine.( refer to Figure 19-1 )
When exit from STOP mode using Internal RC-Oscillated
Watchdog Timer by external interrupt, the oscillation sta-
bilization time is required to normal operation. Figure 19-
4 shows the timing diagram. When release the Internal
RC-Oscillated Watchdog Timer mode, the basic interval
timer is activated on wake-up. It is increased from 00
H
un-
til FF
H
. The count overflow is set to start normal opera-
tion. Therefore, before STOP instruction, user must be set
its relevant prescaler divide ratio to have long enough time
(more than 20msec). This guarantees that oscillator has
started and stabilized.
By reset, exit from STOP mode using internal RC-Oscillat-
ed Watchdog Timer is shown in Figure 19-5 .
~
STOP Mode
Time can not be control by software
Oscillator
(X
IN
pin)
~
~
~
STOP Instruction Execution
Stabilizing Time
t
ST
= 64mS @4MHz
Internal
Clock
Internal
RESET
~
~
~
~
~
RESET
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