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參數(shù)資料
| 型號： | GMS81C1404 |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | IC FLASH MEM 4MBIT 11NS 32-PLCC |
| 中文描述： | 8位單晶片微控制器 |
| 文件頁數(shù)： | 54/93頁 |
| 文件大?。?/td> | 853K |
| 代理商： | GMS81C1404 |
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GMS81C1404/GMS81C1408
52
June. 2001 Ver 1.2
The SPI allows 8-bits of data to be synchronously transmit-
ted and received. To accomplish communication, typically
three pins are used:
- Serial Data In
- Serial Data Out
- Serial Clock
RC5/SIN
RC6/SOUT
RC4/SCK
Additonarlly a fourth pin may be used when in a master or
a slave mode of operation:
- Serial Transfer Ready
RC3/SRDYIN/SRDYOUT
The serial data transfer operation mode is decided by set-
ting the SM1 and SM0 of SPI Mode Control Register, and
the transfer clock rate is decided by setting the SCK1 and
SCK0 of SPI Mode Control Register as shown in Figure
14-1 . And the polarity of transfer clock is selected by set-
ting the POL.
The bit SRDY is used for master / slave selection. If this
bit is set to “1” and SCK[1:0] is set to “11”, the controller
is performed to slave controller. As it were, the port RC3
is served for SRDYOUT.
Figure 14-2 SPI Timing Diagram (without SRDY control)
Figure 14-3 SPI Timing Diagram (with SRDY control)
D1
D2
D3
D4
D6
D7
D0
D5
D1
D2
D3
D4
D6
D7
D0
D5
SIOST
SCK
(POL=1)
SCK
(POL=0)
SOUT
SIN
SPIF
(SPI Int. Req)
D1
D2
D3
D4
D6
D7
D0
D5
D1
D2
D3
D4
D6
D7
D0
D5
SRDY
SIOST
SCK
(POL=1)
SCK
(POL=0)
SOUT
SIN
SPIF
(SPI Int. Req)
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