參數(shù)資料
型號(hào)： GMS81516BT
廠商： Hynix Semiconductor Inc.
英文描述： [General Purpose(1) : ADC/ LED/ SCI/ PWM]
中文描述： [通用（1）：藝術(shù)發(fā)展局/發(fā)光/工商/脈寬調(diào)制]
文件頁(yè)數(shù)： 67/110頁(yè)
文件大?。?/td> 1980K
代理商： GMS81516BT
GMS81508B/16B/24B, GMS82512/16/24
64
MAY. 2001 Ver 2.0
16.3 Multi Interrupt
If two requests of different priority levels are received si-
multaneously, the request of higher priority level is ser-
viced. If requests of the interrupt are received at the same
time simultaneously, an internal polling sequence deter-
mines by hardware which request is serviced.
Figure 16-6 Execution of Multi Interrupt
However, multiple processing through software for special
features is possible. Generally when an interrupt is accept-
ed, the I-flag is cleared to disable any further interrupt. But
as user sets I-flag in interrupt routine, some further inter-
rupt can be serviced even if certain interrupt is in progress.
Example:
During Timer1 interrupt is in progress, INT0 in-
terrupt serviced without any suspend.
TIMER1: PUSH
A
X
Y
IENH,#80H
IENL,#0
PUSH
PUSH
LDM
LDM
EI
:
:
:
;
Enable INT0 only
;
Disable other
;
Enable Interrupt
:
:
:
LDM
LDM
POP
POP
POP
RETI
IENH,#0FFH
IENL,#0F0H
Y
X
A
;
Enable all interrupts
16.4 External Interrupt
The external interrupt on INT0, INT1, INT2 and INT3 pins
are edge triggered depending on the edge selection register
IEDS (address 0F8
H
) as shown in Figure 16-7.
The edge detection of external interrupt has three transition
enable INT0
disable other
TIMER 1
service
INT0
service
Main Program
service
Occur
TIMER1 interrupt
Occur
INT0
EI
enable INT0
enable other
In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable “EI” in the TIMER1 routine.
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