參數(shù)資料
型號(hào)： GMM77332380CNTG-6
英文描述： x72 EDO Page Mode DRAM Module
中文描述： x72 EDO公司頁(yè)面模式內(nèi)存模塊
文件頁(yè)數(shù)： 10/27頁(yè)
文件大小： 401K
代理商： GMM77332380CNTG-6
LG Semicon
GMM77316380CTG-5/6
10
t
HPC
(min) can be achieved during a series of EDO mode early write cycles or EDO mode read
cycles. If both write and read operation are mixed in a EDO mode, RAS cycle { EDO mode mix
cycle (1),(2) } minimum value of CAS cycle t
The value of CAS cycle time of mixed EDO page mode is shown in
HPC
(min) value.
EDO page mode mix cycle (1) and (2).
HPC
(t
CAS
+ t
CP
+ 2t
T
) becomes greater than the
Data output turns off and becomes high impedance from later rising edge of RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between t
OHR
and t
OH
, and between t
OFR
and t
OFF
.
t
DOH
defines the time at which the output level go cross. V
OL
=0.8V, V
OH
=2.0V of output timing
reference level.
Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64
§
period on the condition a and b below.
a. Enter self refresh mode within 15.6
us
after either burst refresh or distributed refresh at equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addressed within 15.6
us
after exiting from self refresh mode.
In case of entering from RAS-only-refresh, it is necessary to execute CBR refresh before and
after self refresh mode according as note 23.
For L_version, it is available to apply each 128
note 23.
At t
RASS
￡
100
us
, self refresh mode is activated, and not activated at t
RASS
￡
10
us
. It is undefined
within the range of 10
us
￡
t
RASS
￡
100
us
. for t
RASS
￡
10
us
, it is necessary to satisfy t
RPS
.
XXX: H or L ( H : V
IH
(min)
<=
V
IN
<=
V
IH
(max), L: V
IH
(min)
<=
V
IN
<=
V
IH
(max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied V
IH
or V
IL.
§
and 31.2
us
instead of 64
§
and 15.6
us
at
20.
21.
22.
23.
24.
25.
26.
27.
相關(guān)PDF資料
PDF描述
GMM77332380CTG-5 x72 EDO Page Mode DRAM Module
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GMM7738280CTG 8Mx72|3.3V|5/6|x 9|FP/EDO DRAM - 64MB Buffered DIMM
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