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參數(shù)資料
| 型號(hào)： | GMM27333230ANTG-8 |
| 英文描述： | x72 SDRAM Module |
| 中文描述： | x72內(nèi)存模塊 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 169K |
| 代理商： | GMM27333230ANTG-8 |
Rev. 1.1/Dec.99
9
GMM27333230ATG
AC Characteristics
(Ta = 0 to 70C, V
CC
, V
CCQ
= 3.3 V +/- 0.3 V, V
SS
, V
SSQ
= 0 V)
(Continued)
Test Condition
Input and output-timing reference levels: 1.4V
Input waveform and output load: See following figures
20%
t
T
t
T
0.4V
2.4V
I/O
80%
OPEN
input
C
L
Notes :1. AC measurement assumes
t
T
= 1ns. Reference level for timing of input signals is 1.40V.
If
t
T
is longer than 1ns,transition time compensation should be considered.
2. Access time is measured at 1.40V. Load condition is C
L
= 50pF without termination.
3.
t
LZ
(min)defines the time at which the outputs achieves the low impedance state.
4.
t
HZ
(max)defines the time at which the outputs achieves the high impedance state.
5.
t
CES
define CKE setup time to CKE rising edge except Power down exit command.
6. The on-DIMM PLL must be given enough clock cycles to stabilize (
t
STAB
) before any
operation can be guaranteed.
Symbol
Notes
Parameter
1
t
RRD
1
Active (a) to Active (b)
command period
Refresh period
t
REF
t
STAB
t
RWL
Write recovery or data-in
to precharge lead time
Unit
ns
ns
ms
6
us
- 7K
Min
Max
10
-
20
-
-
64
- 7J
Min
Max
10
-
20
-
-
64
- 10K
Min
Max
15
-
20
-
-
64
- 8
Min
Max
8
-
16
-
-
64
200
-
200
-
200
-
200
-
PLL Stabilization time
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| GMM27333230ATG-10K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
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| GMM27333230ATG-7J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| GMM27333230ATG-7K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| GMM27333230ATG-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
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