參數(shù)資料
型號(hào): GMM27316230ETG-75
英文描述: x72 SDRAM Module
中文描述: x72內(nèi)存模塊
文件頁數(shù): 7/14頁
文件大?。?/td> 169K
代理商: GMM27316230ETG-75
Rev. 1.1/Dec.99
7
GMM27333230ATG
Notes : 1. I
CC
depends on output load condition when the device is selected. I
CC (
max) is specified at the
output open condition.
2. One bank operation.
3. Addresses are changed once per one cycle.
4. Addresses are changed once per two cycles.
5. After Power down mode, CLK operating current.
6. After Power down mode, no CLK operating current.
7. After self refresh mode set, self refresh current.
8. Input signals are V
IH
or V
IL
fixed.
Input leakage current
I
LI
uA
0<=Vin<=V
CC
Output leakage current
I
LO
uA
0<=Vout <=V
CC
DQ = disable
Output high voltage
V
OH
V
I
OH
= -2 mA
Output low voltage
V
OL
V
I
OL
=2 mA
-1
1
-1.5
1.5
-
0.4
Parameter
Symbol
Unit
Test conditions
Notes
Min
Max
- 8, - 7K, -7J, -10K
2.4
-
Capacitance (Ta = 25C, V
CC
, V
CCQ
= 3.3V +/- 0.3V)
Note :
1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. DQMB = V
IH
to disable Dout.
3. This parameter is sampled and not 100% tested.
Symbol
Parameter
Min
Max
Unit
Notes
C
I1
Input capacitance (A0 ~ A10, BA0)
-
20
pF
1, 3
C
I2
Input capacitance (RAS, CAS, WE, CKE)
-
pF
C
I3
Input capacitance (CK0, CK1, CK2, CK3)
-
pF
C
I4
Input capacitance (S0,S2)
-
pF
C
I5
Input capacitance (DQMB1)
-
pF
C
I/O
I/O capacitance (DQ0 ~ 63, CB0 ~ 7)
-
pF
20
45
20
20
20
1, 3
1, 3
1, 3
1, 3
1, 2, 3
C
I6
Input capacitance (DQMB0, 2, 3, 4, 5, 6, 7)
-
pF
20
1, 3
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