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參數(shù)資料
| 型號： | GM8164 |
| 英文描述： | Serial I/Os Extension Chip(串行I/O擴展芯片) |
| 中文描述： | 串行I / O擴展芯片（串行的I / O擴展芯片） |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 679K |
| 代理商： | GM8164 |
GM8164
Goldtel Micro-Electronics
I/O EXTENSION
4 - 1
1
Introduction
1.1
General Description
GM8164 is a static synchronously serial-input
parallel-output or asynchronously parallel-input
serial-output register, which mainly is for I/Os
extension and completes the following functions:
- Serial-in/Parallel-out, latch output
- Parallel- in/Serial-out
1.2
Features
- Provides 32 Input Pins and 40 Output Pins
- Provides 8 Open-drain Output Pins
- Fully Synchronous Data Transfers
- Typical Shift Frequency 1MHz
- Very Low Power Consumption, 13 μA at
3.3V ,1MHz
- Very Low Quiescent Current, 3 μA at
3.3V
- 2.7V~ 5.6V Operating Voltage Range
- Expandable for n-Bit I/O Applications
-
Serial-in/Parallel-out,
in/Serial-out Register pin function
- GM8164JN: 40 bit output, 32 bit input
GM8164QP: 38 bit output, 32 bit input
Parallel-
1.3
APPLICATION
- I/O Expansion
- Serial Input / Parallel Output
- Parallel Input / Serial Output
- Shift Right Register
- Shift Right with parallel loading
- Address Register
- Buffer Register
- Bus System Register With Enable Parallel
Lines at Bus Side
1.4
DESCRIPTION
The GM8164 is a CMOS device, a static
eight-stage Serial-in, Parallel-out and
Parallel-in, Serial-out register, It can be
used to:
_ convert serial data to parallel form and
direct the parallel data to either of five
buses.
_ store parallel data.
_ accept parallel data from either of five
buses and convert that data to serial form.
_ I/O Inputs that control the operations
include
a single-phase CLOCK (CLK),
DATA LATCH ENABLE (LE),
DATA OUT ENABLE(OC) , and
PARAL LEL/SERIAL (I/O).
_ expand to hundreds I/O ports.
Both the shift and storage clocks are
positive-edge triggered. Data
include 40 parallel data lines of which the
eight O 0-O 7 data lines are inputs (open
drain outputs) and O 8-O 39 data lines are
inputs (outputs) depending on the signal
level on the I/O input. All register stages
are
D-type
master-slave
allowing synchronous or asynchronous
data transfer from master to slave.
Isolation from external noise and the
effects of loading is provided by output
buffering.
inputs
flip-flops
2
Specifications
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