![](http://datasheet.mmic.net.cn/370000/GL646_datasheet_16691643/GL646_11.png)
Revision 1.3
Mar.22 2001
-10-
GL646USB
This signal is applied synchronously with MCLK to specify the point of time that
the input is sampled.
Analog Device type : CDS image sampling clock
BSMP(CDSCLK1)
O
Analog Device type : Black level sampling clock
SCLK
O
Serial interface clock output for Front-end
SENLOAD
O
Serial interface data latch-in signal for Front-end
MCLK(ADCCLK)
O
Wolfson type : Master clock.
This clock is applied at either six or three times the input pixel rate depending on
the operational mode.
Analog Device type: ADC Converter sampling clock
SDI
O
Serial interface data output signal for Front-end
SDO
I
Serial interface data input signal for Front-end
DRAM
DBUS0~15
B
DRAM data bus
ABUS0~8
O
DRAM address bus
RASX
O
DRAM RAS signal of first memory chip
CASX
O
DRAM CAS signal of first memory chip
NOEX
O
DRAM OE(output enable) signal of first memory chip
NWEX
O
DRAM WE signal of first memory chip
RASY
O
DRAM RAS signal of second memory chip
CASY
O
DRAM CAS signal of second memory chip
NOEY
O
DRAM OE(output enable) signal of second memory chip
NWEY
O
DRAM WE signal of second memory chip
Miscellaneous
TSTMOD
TSTSEL0
TSTSEL1
MPU_SEL
I
Test mode selection pins :
{TSTMOD,TSTSEL0,TSTSEL1,MPU_SEL}=
0000 : mode1 0100 : mode2 0011 : mode3 0010 : mode4 0110 : mode5
100x : mode6 110x : mode7 101x : mode8 1110 : mode9
MTR_SEL
I
MTR_SEL=1 select Bi_polar MTR_SEL=0 select Uni_polar
IX1
I
Clock input for crystal
IOX2
O
Clock output for crystal
CKSEL
MPUCLOE
I
Scanner controller clock selection
MPUCLK
O
Clock output
EXTRST_
I
Hardware reset input
POWER
AVDD
P
Analog power input
AVSS
P
Analog ground input
AGND
P
Analog ground input for USB1.1
DVDD
P
Digital power input
DGND
P
Digital ground input