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參數(shù)資料
| 型號： | GD16543-40AB |
| 英文描述： | CLOCK/DATA RECOVERY|QFL|40PIN|CERAMIC |
| 中文描述： | 時鐘/數(shù)據(jù)恢復(fù)| QFL | 40PIN |陶瓷 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 145K |
| 代理商： | GD16543-40AB |
LOS_DET
The Loss Of Signal DETection
(LOS_DET) alarm output is low during
normal operation.
The LOS_DET signal is the output from a
digital Bit Error Flag (BEF) circuit which
monitors the number of false bit transi-
tions in the data signal. A internal flag is
raised if the number of false transitions is
above a predefined level, i.e. if the Bit
Error Rate (BER) is above a predefined
level.
This has been realised with a counter
counting the false bit transitions. If this
counter runs out within a time period the
BEF flag is set. The length of the counter
may be set by external select signals
(SBER0 and SBER1). The time period
that the false errors are counted within is
64kbits corresponding to 26 s at
STM 16 / OC-48 data rate. The length of
the counter may be set to detect bit error
rates of 0.5E-3, 1E-3, 2E-3 or 4E-3.
The input to the BEF circuit is derived
from Bang-Bang detector sample data.
As discussed above, the Bang-Bang de-
tector samples the incoming data twice
each bit period, once at the transition and
once in the middle of the eye. If the value
of the samples in the middle of the eye
for two consecutive bits is equal but the
value of the transition sample is different
then a bit error has occurred.
As the BEF system detects false bit tran-
sitions between two consecutive bits,
only bit errors due to high frequency
noise are detected. Therefore there will
not be a 1:1 correlation between the ac-
tual BER of the signal and the number of
errors detected by the BEF system. The
actual bit error rate is however correlated
to the number of errors detected in the
BEF system. This means that by choos-
ing the appropriate counter length, it will
be possible for the BEF system to set the
BEF flag at a user selectable bit error
rate.
Once the LOS_DET signal has been as-
serted, it will be de-asserted only when
the BER is less than
of the set rate for
a period which is proportional to the se-
lected data rate. (at least 125 s at
STM16 / OC-48).
Peak Level Monitor
An integrated analogue peak level detec-
tor circuit continuously monitors the input
data voltage swing.
The output from this circuit is conditioned
and is available as an analogue output
signal at the MON pin.
Output Disable
It is possible to set the data (SDOP/N)
outputs of the GD16522 to a defined
logic level by using the shutdown input
pins (SDOWN_L and SDOWN_G).
If both shutdown pins are connected to
VEE they have no effect on the data out-
puts.
By setting SDOWN_L to VCC the data
outputs will be latched to give a fixed
logic 1 output if LOCK_DET is asserted.
By setting SDOWN_G to VCC the data
outputs will be latched to give a fixed
logic 1 output regardless of the state of
LOCK_DET and of the setting of
SDOWN_L.
The Shutdown pins have no effect on the
clock (SCOP/N) outputs.
Data Inputs
Limiting Amplifier
The limiting input amplifier is a high per-
formance input data signal conditioning
buffer with sensitivity better than 8 mV.
Data input is CML.
The inputs may be either AC or DC cou-
pled. In both cases input termination is
made through pins DIREF / DIREFN. If
the inputs are AC coupled the amplifier
features an internal offset cancelling DC
feedback. Notice that the offset cancella-
tion will only work when the input is
AC-coupled as shown in the
Figures on
page 4
.
The limiting amplifier inputs are opera-
tional when the SD_SEL input is con-
nected to a logic high (VCC).
Alternatively, the high-speed serial loop-
back input can be selected by connecting
SD_SEL to a logic low (VEE) to allow
loop-back diagnostic testing of the
system.
DEC_ADJ
The DEC_ADJ input can be used to com-
pensate for input data with a non-sym-
metric duty cycle, allowing control over
the DC bias level of the limiting amplifier
output. The DC bias point can be steered
up or down by an external potentiometer.
By this means the optimum data sam-
pling point of the Bang-Bang phase de-
tector can be achieved for duty cycles of
30% to 70%. If the DEC_ADJ pin is un-
connected the DC bias will default to an
internally set level optimised for input
data with a 50% duty cycle.
Peak Level Monitor
(MON and MON_REF)
The MON and MON_REF pins can be
used to indicate the peak level of input
data. An output voltage is available at the
MON pin, which is proportional to the
peak level of the input signal. MON_REF
is an internally generated fixed reference
voltage. The difference between the
value obtained at the MON pin and the
value of MON_REF indicates the peak
input data signal level.
Application data pertaining to use of
MON, MON_REF and DEC_ADJ is avail-
able from GIGAs Application Depart-
ment.
Outputs
Following the CDR block the re-timed
data is output together with the re-
covered clock. The data and clock out-
puts are differential CML with on-chip
50
back termination. The output clock
frequency is related to the selected data
input rate and data output rate (i.e.
2.488 GHz when 2.488 Gbit/s selected;
1.244 GHz when 1.244 Gbit/s selected;
622 MHz when 622 Gbit/s selected;
155 MHz when 155 Gbit/s selected). The
outputs can externally be either AC- or
DC- coupled.
Package
The GD16522 is provided in 48 lead
power enhanced TQFP with heat slug on
bottom surface which is VEE potential.
Data Sheet Rev.: 21
GD16522
Page 3 of 12
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