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參數(shù)資料
| 型號(hào)： | GAL22V10D-15LJ |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | PCB; Leaded Process Compatible:No; PCB Type:4 Channel I/O Rack; Peak Reflow Compatible (260 C):No; Size:3.5 x 3.5 in; Thickness:2.32" RoHS Compliant: No |
| 中文描述： | EE PLD, 15 ns, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 3/18頁(yè) |
| 文件大小： | 223K |
| 代理商： | GAL22V10D-15LJ |
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Specifications
GAL22LV10
3
GAL22LV10 OUTPUT LOGIC MACROCELL (OLMC)
Each of the Macrocells of the GAL22LV10 has two primary func-
tional modes: registered, and combinatorial I/O. The modes and
the output polarity are set by two bits (SO and S1), which are nor-
mally controlled by the logic compiler. Each of these two primary
modes, and the bit settings required to enable them, are described
below and on the following page.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC’s D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an in-
dividual product-term for each OLMC, and can therefore be defined
by a logic equation. The D flip-flop’s /Q output is fed back into the
AND array, with both the true and complement of the feedback
available as inputs to the AND array.
NOTE: In registered mode, the feedback is from the /Q output of
the register, and not from the pin; therefore, a pin defined as reg-
istered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.
COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the output
buffer drive either true (active high) or inverted (active low). Out-
put tri-state control is available as an individual product-term for
each output, and may be individually set by the compiler as either
“on” (dedicated output), “off” (dedicated input), or “product-term
driven” (dynamic I/O). Feedback into the AND array is from the pin
side of the output enable buffer. Both polarities (true and inverted)
of the pin are fed back into the AND array.
The GAL22LV10 has a variable number of product terms per
OLMC. Of the ten available OLMCs, two OLMCs have access to
eight product terms (pins 17 and 27), two have ten product terms
(pins 18 and 26), two have twelve product terms (pins 19 and 25),
two have fourteen product terms (pins 20 and 24), and two OLMCs
have sixteen product terms (pins 21 and 23). In addition to the
product terms available for logic, each OLMC has an additional
product-term dedicated to output enable control.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either active
high or active low.
The GAL22LV10 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two prod-
uct terms are common to all registered OLMCs. The Asynchronous
Reset sets all registers to zero any time this dedicated product term
is asserted. The Synchronous Preset sets all registers to a logic
one on the rising edge of the next clock pulse after this product term
is asserted.
NOTE: The AR and SP product terms will force the Q output of the
flip-flop into the same state regardless of the polarity of the output.
Therefore, a reset operation, which sets the register output to a zero,
may result in either a high or low at the output pin, depending on
the pin polarity chosen.
A R
S P
D
Q
Q
C L K
4 T O 1
M U X
2 T O 1
M U X
Output Logic Macrocell (OLMC)
Output Logic Macrocell Configurations
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GAL22V10D-15LJI | High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10D-15LP | High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10D-15LPI | High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10D-15QJ | High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10C-10LJ | High Performance E2CMOS PLD Generic Array Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GAL22V10D-15LJI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 HI PERF E2CMOS PLD RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| GAL22V10D-15LJN | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 HI PERF E2CMOS PLD RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| GAL22V10D15LJNI | 制造商:Lattice Semiconductor Corporation 功能描述: |
| GAL22V10D-15LJNI | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 HI PERF E2CMOS PLD RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| GAL22V10D-15LP | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5V 22 I/O RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
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