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參數(shù)資料
| 型號(hào)： | GAL22V10C-7LJI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | MR Series Rocker, 1 lamp circuit (Clear Red) miniature rectangle housing, SPDT, 2 position, Quick-connect, Snap-in panel, Silver alloy contacts |
| 中文描述： | EE PLD, 7.5 ns, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 14/18頁(yè) |
| 文件大?。?/td> | 223K |
| 代理商： | GAL22V10C-7LJI |
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Specifications
GAL22LV10
14
Typ. Vref = Vcc
Typical Output
Typ. Vref = Vcc
Typical Input
Circuitry within the GAL22V10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (tpr, 1
μ
s MAX). As a result, the
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the asyn-
chronous nature of system power-up, some conditions must be
met to provide a valid power-up reset of the GAL22V10. First, the
Vcc rise must be monotonic. Second, the clock input must be at
static TTL level as shown in the diagram during power up. The
registers will reset within a maximum of
tpr time. As in normal sys-
tem operation, avoid clocking the device until all input and feed-
back path setup times have been met. The clock must also meet
the minimum pulse width requirements.
Vcc
PIN
Vref
Tri-State
Control
Active Pull-up Circuit
(GAL22LV10D Only)
Feedback
(To Input Buffer)
PIN
Feedback
Data
Output
Vcc
PIN
Vcc
Vref
Active Pull-up Circuit
(GAL22LV10D Only)
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
PIN
Vcc (min.)
t
pr
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
t
wl
t
su
Device Pin
Reset to Logic "0"
Vcc
CLK
INTERNAL REGISTER
Q - OUTPUT
ACTIVE LOW
OUTPUT REGISTER
ACTIVE HIGH
OUTPUT REGISTER
Power-Up Reset
Input/Output Equivalent Schematics
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GAL22V10D-10QJ | Programmable Logic Controller; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No |
| GAL22V10D-10QP | High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10D-15LJ | PCB; Leaded Process Compatible:No; PCB Type:4 Channel I/O Rack; Peak Reflow Compatible (260 C):No; Size:3.5 x 3.5 in; Thickness:2.32" RoHS Compliant: No |
| GAL22V10D-15LJI | High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10D-15LP | High Performance E2CMOS PLD Generic Array Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GAL22V10C-7LP | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10C-7LPI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Electrically-Erasable PLD |
| GAL22V10D-10LD/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable PLD |
| GAL22V10D10LJ | 制造商:Lattice Semiconductor Corporation 功能描述: |
| GAL22V10D-10LJ | 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5V 22 I/O RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
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