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參數(shù)資料
| 型號： | GAL22V10C-10LPI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High Performance E2CMOS PLD Generic Array Logic |
| 中文描述： | EE PLD, 10 ns, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 223K |
| 代理商： | GAL22V10C-10LPI |
Specifications
GAL22LV10
13
Electronic Signature
An electronic signature (ES) is provided in every GAL22LV10
device. It contains 64 bits of reprogrammable memory that can
contain user-defined data. Some uses include user ID codes,
revision numbers, or inventory control. The signature data is al-
ways available to the user independent of the state of the security
cell.
The electronic signature is an additional feature not present in other
manufacturers' 22V10 devices. To use the extra feature of the user-
programmable electronic signature it is necessary to choose a
Lattice Semiconductor 22V10 device type when compiling a set of
logic equations. In addition, many device programmers have two
separate selections for the device, typically a GAL22LV10 and a
GAL22V10-UES (UES = User Electronic Signature) or GAL22V10-
ES. This allows users to maintain compatibility with existing 22V10
designs, while still having the option to use the GAL device's ex-
tra feature.
The JEDEC map for the GAL22LV10 contains the 64 extra fuses
for the electronic signature, for a total of 5892 fuses. However, the
GAL22LV10 device can still be programmed with a standard 22V10
JEDEC map (5828 fuses) with any qualified device programmer.
Security Cell
A security cell is provided in every GAL22LV10 device to prevent
unauthorized copying of the array patterns. Once programmed,
this cell prevents further read access to the functional bits in the
device. This cell can only be erased by re-programming the de-
vice, so the original configuration can never be examined once this
cell is programmed. The Electronic Signature is always available
to the user, regardless of the state of this control cell.
Latch-Up Protection
GAL22LV10 devices are designed with an on-board charge pump
to negatively bias the substrate. The negative bias is of sufficient
magnitude to prevent input undershoots from causing the circuitry
to latch.
Device Programming
GAL devices are programmed using a Lattice Semiconductor-
approved Logic Programmer, available from a number of manu-
facturers (see the the GAL Development Tools section). Complete
programming of the device takes only a few seconds. Erasing of
the device is transparent to the user, and is done automatically as
part of the programming cycle.
Typical Input Pull-up Characteristic
Input Voltage (V)
I
-80
-70
-60
-50
-40
-30
-20
-10
0
0
0
1
1
2
2
3
3
4
Output Register Preload
When testing state machine designs, all possible states and state
transitions must be verified in the design, not just those required
in the normal machine operations. This is because certain events
may occur during system operation that throw the logic into an
illegal state (power-up, line voltage glitches, brown-outs, etc.). To
test a design for proper treatment of these conditions, a way must
be provided to break the feedback paths, and force any desired (i.e.,
illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.
The GAL22LV10 device includes circuitry that allows each regis-
tered output to be synchronously set either high or low. Thus, any
present state condition can be forced for test sequencing. If nec-
essary, approved GAL programmers capable of executing test
vectors perform output register preload automatically.
Input Buffers
GAL22LV10 devices are designed with TTL level compatible input
buffers. These buffers have a characteristically high impedance,
and present a much lighter load to the driving logic than bipolar TTL
devices.
The input and I/O pins on the GAL22LV10D also have built-in active
pull-ups. As a result, floating inputs will float to a TTL high (logic
1). However, Lattice Semiconductor recommends that all unused
inputs and tri-stated I/O pins be connected to an adjacent active
input, Vcc, or ground. Doing so will tend to improve noise immu-
nity and reduce Icc for the device. (See equivalent input and I/O
schematics on the following page.)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GAL22V10C-10LR/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable PLD |
| GAL22V10C-15LJI | 制造商:Lattice Semiconductor Corporation 功能描述: |
| GAL22V10C-15LPI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10C-5LJ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10C-7LJ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High Performance E2CMOS PLD Generic Array Logic |
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