- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370306 > GAL22V10B-25LJI (LATTICE SEMICONDUCTOR CORP) High Performance E2CMOS PLD Generic Array Logic PDF資料下載
參數(shù)資料
| 型號： | GAL22V10B-25LJI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High Performance E2CMOS PLD Generic Array Logic |
| 中文描述： | EE PLD, 25 ns, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 7/18頁 |
| 文件大小： | 223K |
| 代理商： | GAL22V10B-25LJI |
SSpecifications
GAL22LV10D
7
-5
MIN. MAX.
t
pd
2
t
co
2
t
cf
3
t
su
t
h
A
Input or I/O to Combinational Output
1
4
1
5
ns
A
Clock to Output Delay
1
3
1
3.5
ns
—
Clock to Feedback Delay
—
2.5
—
3
ns
—
Setup Time, Input or Feedback before Clock
↑
3
—
3.5
—
ns
—
A
Hold Time, Input or Feedback after Clock
↑
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
0
—
—
0
—
—
ns
MHz
167
143
f
max
4
A
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
182
—
154
—
MHz
A
Maximum Clock Frequency with
No Feedback
250
—
200
—
MHz
t
wh
4
t
wl
4
t
en
t
dis
t
ar
t
arw
t
arr
t
spr
—
Clock Pulse Duration, High
2
—
2.5
—
ns
—
Clock Pulse Duration, Low
2
—
2.5
—
ns
B
Input or I/O to Output Enabled
1
5
1
6
ns
C
Input or I/O to Output Disabled
1
5
1
6
ns
A
Input or I/O to Asynchronous Reset of Register
1
4.5
1
5.5
ns
—
Asynchronous Reset Pulse Duration
4.5
—
5.5
—
ns
—
Asynchronous Reset to Clock
↑
Recovery Time
3.5
—
4
—
ns
—
Synchronous Preset to Clock
↑
Recovery Time
3.5
—
4
—
ns
-4
MIN. MAX.
UNITS
PARAMETER
TEST
COND
1
.
DESCRIPTION
SYMBOL
PARAMETER
TYPICAL
UNITS
TEST CONDITIONS
C
I
Input Capacitance
5
pF
V
CC
= 3.3V, V
I
= 0V
C
I/O
I/O Capacitance
5
pF
V
CC
= 3.3V, V
I/O
= 0V
1) Refer to
Switching Test Conditions
section.
2) Minimum values for
t
pd and
t
co are not 100% tested but established by characterization.
3) Calculated from
f
max with internal feedback. Refer to
fmax Descriptions
section.
4) Refer to
fmax Descriptions
section. Characterized but not 100% tested.
COM
COM
AC Switching Characteristics
Over Recommended Operating Conditions
Capacitance (T
A
= 25
°
C, f = 1.0 MHz)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GAL22V10D-25LPI | High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10B-25LPI | High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10D-20LJI | High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10D-20LPI | High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10D-25LJ | High Performance E2CMOS PLD Generic Array Logic |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GAL22V10B-25LP | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10B-25LPI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10B-25QJ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10B-25QP | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10B-30LD/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable PLD |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。