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參數(shù)資料
| 型號： | GAL22V10B-15LJI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | SerDes Gigabit Ethernet Transceiver |
| 中文描述： | EE PLD, 15 ns, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 9/18頁 |
| 文件大小： | 223K |
| 代理商： | GAL22V10B-15LJI |
SSpecifications
GAL22LV10C
9
t
pd
2
t
co
2
t
cf
3
t
su
t
h
A
Input or I/O to Combinatorial Output
2
7.5
2
10
2
15
ns
A
Clock to Output Delay
1
5
1
6.5
1
10
ns
—
Clock to Feedback Delay
—
3
—
5
—
5
ns
—
Setup Time, Input or Fdbk before Clk
↑
6
—
7.5
—
10
—
ns
—
Hold Time, Input or Fdbk after Clk
↑
0
—
0
—
0
—
ns
A
Maximum Clock Frequency with
External Feedback, 1/(tsu + tco)
91
—
71
—
50
—
MHz
f
max
4
A
Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
111
—
80
—
66
—
MHz
A
Maximum Clock Frequency with
No Feedback
125
—
111
—
83
—
MHz
t
wh
t
wl
t
en
t
dis
t
ar
t
arw
t
arr
t
spr
—
Clock Pulse Duration, High
3.5
—
4
—
6
—
ns
—
Clock Pulse Duration, Low
3.5
—
4
—
6
—
ns
B
Input or I/O to Output Enabled
2
10
2
12
2
15
ns
C
Input or I/O to Output Disabled
2
10
2
12
2
15
ns
A
Input or I/O to Asynch. Reset of Reg.
2
11
2
13
2
20
ns
—
Asynch. Reset Pulse Duration
6
—
8
—
10
—
ns
—
Asynch. Reset to Clk
↑
Recovery Time
6
—
8
—
10
—
ns
—
Synch. Preset to Clk
↑
Recovery Time
6
—
8
—
10
—
ns
-15
MIN. MAX.
-10
MIN. MAX.
UNITS
PARAM
TEST
COND.
1
DESCRIPTION
COM
COM
-7
MIN. MAX.
COM
1) Refer to
Switching Test Conditions
section.
2) Minimum values for
t
pd and
t
co are not 100% tested but established by characterization.
3) Calculated from
f
max with internal feedback. Refer to
fmax Description
section.
4) Refer to
fmax Description
section.
SYMBOL
PARAMETER
TYPICAL
UNITS
TEST CONDITIONS
C
I
Input Capacitance
8
pF
V
CC
= 3.3V, V
I
= 0V
C
I/O
I/O Capacitance
8
pF
V
CC
= 3.3V, V
I/O
= 0V
AC Switching Characteristics
Over Recommended Operating Conditions
Capacitance (T
A
= 25
°
C, f = 1.0 MHz)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GAL22V10B-15LP | High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10C-5LJ | High Performance E2CMOS PLD Generic Array Logic |
| GAL22V10B-15LPI | Electrically-Erasable PLD |
| GAL22V10B-15QP | Electrically-Erasable PLD |
| GAL22V10D-15QP | Electrically-Erasable PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GAL22V10B15LP | 制造商:LATTICE 功能描述:* |
| GAL22V10B-15LP | 制造商:Lattice Semiconductor Corporation 功能描述: |
| GAL22V10B-15LPI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Electrically-Erasable PLD |
| GAL22V10B-15LR/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable PLD |
| GAL22V10B-15QJ | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High Performance E2CMOS PLD Generic Array Logic |
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