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參數(shù)資料
| 型號(hào)： | GA81032T-150T |
| 英文描述： | x32 Fast Synchronous SRAM |
| 中文描述： | X32號(hào)，快速同步SRAM |
| 文件頁(yè)數(shù)： | 19/23頁(yè) |
| 文件大?。?/td> | 756K |
| 代理商： | GA81032T-150T |
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Rev: 1.00 12/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
19/23
2000, Giga Semiconductor, Inc.
GS81032T/Q-150/138/133/117/100/66
Sleep Mode Timing Diagram
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of “dummy read cycles” (read cycles that are launched normally, but that are ended with the output
drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there
will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on
dummy cycles, and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address
boundary crossings), but greater care must be exercised to avoid excessive bus contention.
CK
ADSP
ADSC
tH
tKH tKL
tKC
tS
ZZ
tZZR
tZZH
tZZS
~
~
~
~
Snooze
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