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參數(shù)資料
| 型號(hào)： | G768 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | Remote/Local Temperature Sensor, 2 Fan Controllers with SMBus Serial Interface and System Reset Circuit |
| 中文描述： | 遠(yuǎn)程/本地溫度傳感器，2個(gè)風(fēng)扇，帶有SMBus串行接口和系統(tǒng)復(fù)位電路控制器 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 370K |
| 代理商： | G768 |
Ver: 1.3
Oct 28, 2002
TEL: 886-3-5788833
http://www.gmt.com.tw
11
G768B
Global Mixed-mode Technology Inc.
If the remote channel is shorted (DXP to DXN or DXP
to GND), the ADC reads 0000 0000 so as not to trip
either the THIGH or TLOW alarms at their POR set-
tings. In applications that are never subjected to 0°C in
normal operation, a 0000 0000 result can be checked
to indicate a fault condition in which DXP is acciden-
tally short circuited. Similarly, if DXP is short cir-
cuited to V
CC
, the ADC reads +127°C for both remote
and local channels, and the device alarms.
ALERT Interrupts
The ALERT interrupt output signal is latched and can
only be cleared by reading the Alert Response ad-
dress. Interrupts are generated in response to THIGH
and TLOW comparisons and when the remote diode is
disconnected (for continuity fault detection). The in-
terrupt does not halt automatic conversions; new tem-
perature data continues to be available over the SMBus
interface after ALERT is asserted. The interrupt output
rupt output pin is open-drain so that device can share
a common interrupt line. The interrupt rate can never
exceed the conversion rate.
The interface responds to the SMBus Alert Response
address, an interrupt pointer return-address feature
(see Alert Response Address section). Prior to taking
corrective action, always check to ensure that an in-
terrupt is valid by reading the current temperature.
Alert Response Address
The SMBus Alert Response interrupt pointer provides
quick fault identification for simple slave devices that
lack the complex, expensive logic needed to be a bus
master. Upon receiving an ALERT interrupt signal, the
host master can broadcast a Receive Byte transmission
to the Alert Response slave address (0001 100). Then
any slave device that generated an interrupt attempts to
identify itself by putting its own address on the bus.
Table 4. Command-Byte Bit Assignments
REGISTER
RRTE2
RRTE1
RSL
RCL
RCRA
RRHI2
RRLS2
RRHI1
RRLS1
WCA
WCRW
WRHA2
WRLN2
WRHA1
WRLN1
OSHT
SET_CNT1
ACT_CNT1
FAN_STA1
SET_CNT2
ACT_CNT2
FAN_STA2
CHIP_TMP
TMAX1
THYST1
TMAX2
THYST2
COMMAND
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
20h
21h
22h
30h
31h
32h
33h
34h
POR STATE
0000 0000b
0000 0000b
N/A
0000 0000b
0000 0010b
0111 1111b (127) Read 2nd remote THIGH limit
1100 1001b(-55) Read 2nd remote TLOW limit
0111 1111b (127) Read 1st remote THIGH limit
1100 1001b (-55) Read 1st remote TLOW limit
N/A
Write configuration byte
N/A
Write conversion rate byte
N/A
Write 2nd remote THIGH limit
N/A
Write 2nd remote TLOW limit
N/A
Write 1st remote THIGH limit
N/A
Write 1st remote TLOW limit
N/A
One-shot command (use send-byte format)
1111 1111b
Write 1st fan programmed speed register
1111 1111b
Read 1st fan actual speed register
10b
Read 1st fan status register
1111 1111b
Write 2nd fan programmed speed register
1111 1111b
Read 2nd fan actual speed register
10b
Read 2nd fan status register
0000 0000b
On-chip temperature
0100 0110b (70)
1st remote Tmax
0011 1100b (60)
1st remote Thyst
0100 0110b (70)
2nd remote Tmax
0011 1100b (60)
2nd remote Thyst
FUNCTION
Read 2nd remote temperature: returns latest temperature
Read 1st remote temperature: returns latest temperature
Read status byte (flags, busy signal)
Read configuration byte
Read conversion rate byte
The Alert Response can activate several different slave
devices simultaneously, similar to the SMBus General
Call. If more than one slave attempts to respond, bus
arbitration rules apply, and the device with the lower
address code wins. The losing device does
not generate an acknowledge and continues to hold the
ALERT
line low until serviced (implies that the host
interrupt input is level sensitive). Successful reading of
the alert response address clears the interrupt latch.
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