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參數(shù)資料
| 型號： | G709E2-5 |
| 英文描述： | G709E2-5 2.5 Gbits/sec ITU G.709 Reed-Solomon Encoder Core |
| 中文描述： | G709E2 - 5 2.5 Gbits / sec的國際電聯(lián)支持G.709的Reed - Solomon編碼器核心 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 142K |
| 代理商： | G709E2-5 |
comtech
aha
corporation
PSFECEncoderCore_0702
A subsidiary of Comtech Telecommunications Corporation
Page 1 of 2
1.0
INTRODUCTION
This G.709-2.5 core implements the RS(255,239)
code specified in Annex A of the ITU G.709
standard. It is designed to efficiently perform the
Reed Solomon encoding function specified by the
standard. The core requires no configuration, no
initialization, and no resynchronization procedure.
1.1
FEATURES
PERFORMANCE:
ITU G.709 Compatible Reed Solomon core
2.5 Gbits/sec operation in 0.13 micron CMOS
process with 332 MHz clock
One-edge, one clock fully synchronous design
Two clock latency
1K gates
Only initialization is a RESET
8 bit input and output data interfaces
DELIVERABLES:
ITU G.709 compatible RS Encoder core VHDL
Timing constraints (Design Compiler and Ambit
format)
Test bench and verification vectors (VHDL)
2.0
FUNCTIONAL DESCRIPTION
Figure 1:
BLOCK DIAGRAM
2.1
ENCODING
Uncoded block length is 239 Bytes with 16
check Bytes and a correction power of 8 Bytes per
block. Latency through the encoder is two clocks. A
global reset clears all of the flip-flops involved with
generating the parity check bytes.
Processing begins by applying the first data
byte on the DATA bus, asserting the START signal,
and then asserting the CLK signal. Every input byte
is then added with the REG15 output and the sum
input to all the Galois Field constant multipliers
(GFMx). The outputs of these multipliers are
summed with the previous stage value and clocked
into the next register stage. After processing all 239
bytes in this manner the 16 parity check bytes are
strobed out. This process of strobing out the parity
check bytes reinitializes the register stages in
preparation for processing the next block, thus not
requiring any additional RESET pulses.
2.2
REED SOLOMON CODE PARAMETERS
generator polynomial:
where
α
is a root of the binary primitive
polynomial x
8
+ x
4
+ x
3
+ x
2
+ 1 .
Parity bytes are represented by:
R z
( )
R
15
z
15
=
where R
j
(j = 0 to 15) is the parity byte
represented by an element out of GF(256) and R
15
corresponds to the byte 240 in the FEC sub-row and
R
0
to byte 255.
AHAG709-2.5 FEC Encoder
CLK
RESET
START
DATA[7:0]
OUT[7:0]
G z
( )
z
α
i
–
(
)
i
0
=
15
∏
=
R
14
z
14
…
R
1
z
1
R
0
+
+
+
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