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參數(shù)資料
| 型號(hào)： | G709D2-5 |
| 英文描述： | G709D2-5 2.5 Gbits/sec ITU G.709 Reed-Solomon Decoder Core |
| 中文描述： | G709D2 - 5 2.5 Gbits / sec的國(guó)際電聯(lián)支持G.709里德所羅門(mén)解碼器核心 |
| 文件頁(yè)數(shù)： | 2/2頁(yè) |
| 文件大小： | 112K |
| 代理商： | G709D2-5 |
comtech
aha
corporation
A subsidiary of Comtech Telecommunications Corporation
PBG709D10_0203
2003 Comtech AHA Corp.
comtech
aha
corporation
2345 NE Hopkins Court
tel: 509.334.1000
e-mail: sales@aha.com www.aha.com
fax: 509.334.9000
Pullman, WA 99163-5601
INPUT SIGNALS
clk
- 166 MHz core clock. All inputs are registered
on the rising edge.
reset
- Synchronous reset.
received_data[63:0]
- Received data bus. Data bus
is valid every clock and is registered on the
rising edge of
clk
. The data frame is restarted
whenever
start
is active. The core accepts 8-
bytes per transfers
start
- Signal is active to when the first 8 bytes of
the G.709 frame in on the
received_data
bus.
Must be inactive on all other data transfers in
the frame. Maybe asserted at anytime of the
data frame needs to be reset to the first transfer.
fifo_data[63:0]
- FIFO data. Delay version of the
received_data
data stream. The bus is
registered on the rising edge of
clk
.
OUTPUT SIGNALS
decode_complete
- Decoding complete. Active
when the first 8-byte transfer of the G.709
frame is on the
decode_data
data bus and
inactive on all subsequent transfers.
decoded_data[63:0]
- Decoded data. The first 8-
bytes of the corrected G.709 frame are valid
when
decode_complete
is active and the
remainder of the frame is available over the
subsequent 509 clocks. The data is driven from
the rising edge of
clk
.
status_valid
- Status valid signal. Active for a
single
clk
following the completion of the
frame to indicate when the
uncorrectable
,
correct-to-zero
, and
correct_to_one
signals
are valid.
uncorrectable[15:0]
- Uncorrectable block flags.
Each bit of the signal corresponds to one of the
16 Reed-Solomon blocks in the G.709 frame.
Valid when
status_valid
is active.
correct_to_zero[10:0]
- Number of bits corrected
from ‘1’ to ‘0’ in the just completed G.709
frame. Signal is valid when
status_valid
is
active.
correct_to_one[10:0]
- Number of bits corrected
from ‘0’ to ‘1’ in the just completed G.709
frame. Signal is valid when
status_valid
is
active.
DELIVERABLES
G.709D-10 FEC core (VHDL)
Timing constraints (DesignCompiler and Ambit
format)
Test bench and verification vectors (VHDL)
Single use license to AHA’s Reed-Solomon
Patents
PATENTS
Design uses one or more of the following US
Patents: 5,170,399; 5,099,482; 4,873,688;
5,396,502
CONTACT INFORMATION
Comtech AHA Corporation
2345 NE Hopkins Court
Pullman WA 99163
(509) 336-7115
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參數(shù)描述 |
|---|---|
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