
Ver: 1.0
Jan 23, 2003
TEL: 886-3-5788833
http://www.gmt.com.tw
4
G576
Global Mixed-mode Technology Inc.
Logic Section
PARAMETER
TEST CONDITION*
MIN
MAX UNIT
Logic input current
1
A
Logic input high level
2
V
Logic input low level
0.8
V
VCC5=5V, IO=1mA
VCC5 -0.4
Logic output high level
VCC5=0V, IO=1mA, VCC3=3.3V
VCC3 -0.4
V
Logic output low level
IO=1mA
0.4
V
*Pulse-testing techniques maintain junction temperature close to ambient temperatures; thermal effects must be taken into account sepa-
rately.
Switching Characteristics **
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VO (AVCC/BVCC)
2.6
tr
Rise times, output
VO (AVPP/BVPP)
10
VO (AVCC/BVCC)
7.5
tf
Fall times, output
VO (AVPP/BVPP)
38
ms
ton
14
VI (AVPPD0/BVPPD0) to VO (AVPP/BVPP)
toff
44
ton
3.2
VI (
1
AVCCD
/
1
BVCCD
) to VO(AVCC/BVCC) (3.3V)
toff
17
ton
4.4
tpd Propagation delay
(see Figure 1)
VI (
0
AVCCD
/
0
BVCCD
) to VO(AVCC/BVCC) (5V)
toff
20
ms
**Switching Characteristics are with CL = 147F.
§ Refer to Parameter Measurement Information
Parameter Measurement Information
Figure 1. Test Circuits and Voltage Waveforms
Table of Timing Diagrams
FIGURE
AVCC/BVCC Propagation Delay and Rise Time With 1F Load, 3.3V Switch
2
AVCC/BVCC Propagation Delay and Fall Time With 1F Load, 3.3V Switch
3
AVCC/BVCC Propagation Delay and Rise Time With 147F Load, 3.3V Switch
4
AVCC/BVCC Propagation Delay and Fall Time With 147F Load, 3.3V Switch
5
AVCC/BVCC Propagation Delay and Rise Time With 1F Load, 5V Switch
6
AVCC/BVCC Propagation Delay and Fall Time With 1F Load, 5V Switch
7
AVCC/BVCC Propagation Delay and Rise Time With 147F Load, 5V Switch
8
AVCC/BVCC Propagation Delay and Fall Time With 147F Load, 5V Switch
9
AVPP/BVPP Propagation Delay and Rise Time With 1F Load, 12V Switch
10
AVPP/BVPP Propagation Delay and Fall Time With 1F Load, 12V Switch
11
AVPP/BVPP Propagation Delay and Rise Time With 147F Load, 12V Switch
12
AVPP/BVPP Propagation Delay and Fall Time With 147F Load, 12V Switch
13
LOAD CIRCUIT
V
DD
GND
50%
90%
t
off
t
on
10%
V
I(12V)
GND
V
O(AVPP)
AVPP
C
L
VOLTAGE WAVEFORMS
50%
V
I(VPPD0)
(V
I(VPPD1)=0V)
LOAD CIRCUIT
V
DD
GND
50%
90%
t
off
t
on
10%
V
I(3.3V)
GND
V
O(AVCC)
AVCC
C
L
VOLTAGE WAVEFORMS
V
I(VCCD1)
(V
I(VCCD0)=VDD)
50%