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參數(shù)資料
| 型號： | G569CS8U |
| 廠商： | Global Mixed-mode Technology Inc. |
| 英文描述： | CD-RW Laser Diode Current Driver |
| 中文描述： | CD - RW激光二極管電流驅(qū)動器 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 185K |
| 代理商： | G569CS8U |
Ver: 1.0
Oct 02, 2000
TEL: 886-3-5788833
http://www.gmt.com.tw
3
G569C
Global Mixed-mode Technology Inc.
Pin Description
PIN NO. PIN NAME I/O
PIN FUNCTION
1
IW_IN
I
A diode of type BAS216 should be connected between this pin and node IW. This pin provides
the path for sinking IW current.
2
LS_DELTA
O
Connect a 10
Ω resistor from this pin to VSS
3
TST1
I
Test pin. Connect to ground for normal operation.
4
PWO
O
DAC output, connect to PWO_I through a resistor divider
5
DALPHA
I
Control voltage input
6
PWO_I
I
Control voltage input
7
PWB
O
Voltage output
8
PWMAX
O
Voltage output
9
PWMIN
O
Voltage output
10
/RESET
I
Logic input. A Low on this pin reset all DAC latches to 0.
11,42
VSS
I
Ground pin
12
EDB
O
Connect to the base node of external PNP BJT (Type BC808).
13
LS_ERASE
I
Connect a 6.8
Ω (1206 type) resistor from this pin to V
DD
14
PERASE
O
Connect a DAC resistor array from this pin to VSS
15
RECORD
I
Logic input, a high indicates in recording mode.
16
CDR
I
Logic input, a high indicates in CD-R mode.
17
S2V9
I
Voltage input. Contribute to current output on CAGAIN pin and provides internal DAC reference
voltage.
18
CAGAIN2
O
Tristate output. Connect 62K
Ω to pin CAGAIN.
19
CAGS_I
I
Logic input, 0~2V swing.
20
DCAGAIN
O
An optional resistor may be added to modify the output current on CAGAIN
21
CAGAIN
O
Current output
22
RCAGAIN1
O
A 16.2K
Ω resistor should be connected from this pin to VSS
23
RCAGAIN2
O
A 3.9K
Ω resistor should be connected from this pin to VSS
24
PRFINE
O
DAC output, connect to PR_I through a resistor divider
25
PRCOARSE
O
DAC output, connect to PR_I through a resistor divider
26
IR
O
Read current output for laser diode
27
LS_READ
I
Connect two 22
Ω (1206 type) resistors from this pin to V
DD
28
PR_I
I
Voltage input which controls the current on IR pin
29
SELN4_IN
I
Logic input. This pin can be shorted to pin CDR or be connected to the voltage divider formed by
CDR and SELN4.
30,38
VDD
I
Supply voltage input. Each VDD pin should have a 0.1F bypass capacitor to VSS.
31
FSRS
I
Logic input, when FSRS=1, the voltage on pin FSCLR is sampled onto pin FSR, else FSR is in hold
mode.
32
FSR
O
Sampled voltage output, controlled by FSRS
33
IFSA
I
If internal integration control circuitry is used, connect a photo diode from this pin to +30V. connect it
to VDD otherwise
34
FSW
O
Sampled voltage output, controlled by FSWS
35
FSCLR
O
Sampling capacitors and resistor are connected to this pin.
36
FSWS
I
Logic input, when FSWS=1, the voltage on pin FSCLR is sampled onto pin FSW, else FSW is in
hold mode.
37
FSOF
I
If internal integration control circuitry is used, connect the control signal to this pin. A logic low enable
the current charging on the capacitors on pin FSCLR with the current from IFSA. Connect this pin to
VDD if internal integration control circuitry is not used.
39
VI+
I
Non-inverting input of Op Amp
40
VI-
I
Inverting input of Op Amp
41
VOUT
O
Op Amp output
43
CLK
I
Clock input of I
2S bus
44
DI
I
Data input of I
2S bus
45
LD
I
Latch data input of I
2S bus
46
PWRITE
O
Connect a DAC resistor network from this pin to VSS
47
LS_WRITE
I
Connect a 6.8
Ω (1206type) from this pin to V
DD
48
WDB
O
Connect to the base node of external PNP BJT. (Type BC807-40)
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