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參數(shù)資料
| 型號(hào)： | G2996 |
| 英文描述： | DDR Termination Regulator with STR function.|Terminator Series |
| 中文描述： | 復(fù)員與STR函數(shù)終端調(diào)節(jié)。|終結(jié)者系列 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 323K |
| 代理商： | G2996 |
Ver: 1.0
May 23, 2003
TEL: 886-3-5788833
http://www.gmt.com.tw
7
G2996
Global Mixed-mode Technology Inc.
Pin Description
NUMBER
1
2
NAME
GND
SD
FUNCTION
Ground
Active low shutdown control pin
3
4
5
6
7
8
VSENSE
VREF
VDDQ
AVIN
PVIN
VTT
Feedback pin for regulating V
TT
Buffered output that is a reference output of VDDQ/2
Input for internal reference which equals to VDDQ/2
Analog input pin
Power input pin
Output voltage for connection to termination resistors, equal to VDDQ/2
Block Diagram
Description
The G2996 is a linear bus termination regulator de-
signed to meet the JEDEC SSTL-2 and SSTL-3 (Se-
ries Stub Termination Logic) specifications for termi-
nation of DDR-SDRAM. The output, V
TT
, is capable of
sinking and sourcing current while regulating the out-
put voltage equal to VDDQ/2. The G2996 is designed
to maintain the excellent load regulation and with fast
response time to minimum the transition preventing
shoot-through. The G2996 also incorporates two dis-
tinct power rails that separates the analog circuitry
(AVIN) from the power output stage (PVIN). This
power rails split can be utilized to reduce the internal
power dissipation. And this also permits G2996 to pro-
vide a termination solution for the next generation of
DDR-SDRAM (DDR II).
Series Stub Termination Logic (SSTL) was created to
improve signal integrity of the data transmission
across the memory bus. This termination scheme is
essential to prevent data error from signal reflections
while transmitting at high frequencies encountered
with DDR-SDRAM. The most common form of termi-
nation is Class II single parallel termination. This in-
volves one RS series resistor from the chipset to the
memory and one RT termination resistor, both 25
typically. The resistors can be changed to scale the
current requirements from the G2996. This implemen-
tation can be seen below in Figure 1.
AVIN, PVIN
AVIN and PVIN are two independent input supply pins
for the G2996. AVIN is used to supply all the internal
analog circuits. PVIN is only used to supply the output
stage to create the regulated V
TT
. To keep the regula-
tion successfully, AVIN should be equal to or larger
than PVIN. Using a higher PVIN voltage will produce a
larger sourcing capability from V
TT.
But the internal
power loss will also increase and then the heat in-
creases. If the junction temperature exceeds the
thermal shutdown threshold than the G2996 will enter
the shutdown state that is the same as manual shut-
down, where V
TT
is tri-state and V
REF
remains active.
For SSTL-2 applications, the AVIN and PVIN can be
short together at 2.5V to minimize the PCB complexity
and to reduce the bypassing capacitors for the two
supply pins separately.
-
-
PV
IN
AV
IN
V
DDQ
SD
50k
50k
GND
V
REF
V
SENSE
V
TT
+
+
V
DD
CHIPSET
R
S
V
TT
R
T
MENORY
V
REF
Figure 1. SSTL-Termination Scheme
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| G2996F1U | 制造商:GMT 制造商全稱(chēng):Global Mixed-mode Technology Inc 功能描述:DDR I/II Termination Regulator |
| G2996F1UF | 制造商:GMT 制造商全稱(chēng):Global Mixed-mode Technology Inc 功能描述:DDR I/II Termination Regulator |
| G2996P1U | 制造商:GMT 制造商全稱(chēng):Global Mixed-mode Technology Inc 功能描述:DDR I/II Termination Regulator |
| G2996P1UF | 制造商:GMT 制造商全稱(chēng):Global Mixed-mode Technology Inc 功能描述:DDR I/II Termination Regulator |
| G2997 | 制造商:GMT 制造商全稱(chēng):Global Mixed-mode Technology Inc 功能描述:DDR Termination Regulator |
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