參數(shù)資料
型號(hào)： FZE1658G
廠商： INFINEON TECHNOLOGIES AG
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PDSO24
封裝： PLASTIC, DSO-24
文件頁(yè)數(shù)： 14/18頁(yè)
文件大?。?/td> 406K
代理商： FZE1658G
FZE 1658G
Semiconductor Group
5
Circuit Description
In IEC 65A, the following values are specified for 24-VDC input stages of type 2:
The current in the input circuit is determined by the switching element in state “0” and by
characteristics of the input stage in state “1”.
The octal input device FZE 1658G is intended for a configuration comprising two
specified external resistors per channel, as shown in the block diagram. As a result the
power dissipation within the P-DSO-24-1 package is at a minimum.
The voltage dependent current through the external resistor
R
EXT is compensated by a
negative differential resistance of the current sink across pins E and L, therefore input D
behaves like a constant current sink.
The comparator assigns level 1 or 0 to the voltage present at input E. To improve
interference protection, the comparator is provided with hysteresis and a delay element.
A status LED is connected in series with the input circuit (
R
EXT and current sink). The
LED drive short-circuits the status LED if the comparator detects “0”. A constant current
sink in parallel with the LED reduces the operating current of the LED, and a voltage
limiter ensures that the input circuit remains operational if the LED is interrupted. The
specified switching thresholds may change if the LED is interrupted.
For each channel a digital filter is provided which samples the comparator signal at a rate
provided by the clock oscillator. The digital filter is designed as a 5-section shift register.
If any four out of 5 sampling values are identical, the output S changes to the
corresponding state.
On a falling edge at input LO-N, the parallel data S0 - S7 are clocked into the output shift
register. The data can be shifted out serially to the output SO-N by the clock signal T,
with a “1” at the input being represented by a L-signal at the output SO-N. The serial
interface of the shift register fits the synchronous interface of the 8051 microcontroller
(see diagram Serial Data Output Function). By connecting output SO-N to input SE-
N of the next device, several FZE 1658G can be cascaded (see Application Circuit).
SO-N is designed as an open-drain output. SE-N has an internal pull-up current source.
Inputs SE-N, T and SO-N have Schmitt trigger characteristics. The device has separate
ground pins for the input circuitry (GND) and for the logic (DGND). If the supply voltage
falls below
V
USR or CT is connected to DGND, the output shift register will be cleared and
the output SO-N disabled. If the supply voltage is too low, the LED drives will also be
disabled, i.e. the LED lights as soon as current flows in the input circuit.
Level
Input Voltage
Input Current
1
0
min. 11 V
max. 11 V
or max. 5 V
min. 6 mA
max. 2 mA
相關(guān)PDF資料
PDF描述
G15B-11-02 11 CONTACT(S), ALUMINUM, CADMIUM PLATED, FEMALE, CIRCULAR CONNECTOR
G18B-1-01 1 CONTACT(S), ALUMINUM, CADMIUM PLATED, FEMALE, CIRCULAR CONNECTOR
G18S-19-02 19 CONTACT(S), ALUMINUM, CADMIUM PLATED, MALE, CIRCULAR CONNECTOR
G30S-2-01 2 CONTACT(S), ALUMINUM, CADMIUM PLATED, MALE, CIRCULAR CONNECTOR
G30S-4-01 4 CONTACT(S), ALUMINUM, CADMIUM PLATED, MALE, CIRCULAR CONNECTOR
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FZE3-10M20 制造商:Panduit Corp 功能描述:SC TO LC, OM4 STD, RISER, DUPLEX, 1.6MM - Bulk
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