參數(shù)資料
型號(hào)： FXMAR2104UMX
廠商： Fairchild Semiconductor
文件頁(yè)數(shù)： 3/15頁(yè)
文件大?。?/td> 0K
描述： TRANSLATOR 4BIT DUAL 12-UMLP
標(biāo)準(zhǔn)包裝： 5,000
邏輯功能： 變換器，雙向，3 態(tài)，開(kāi)路漏極
位數(shù)： 4
輸入類型： 電壓
輸出類型： 電壓
數(shù)據(jù)速率： *
通道數(shù)： 4
輸出/通道數(shù)目： 1
差分 - 輸入:輸出： 無(wú)/無(wú)
傳輸延遲（最大）： 4ns
電源電壓： 1.65 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
封裝/外殼： *
供應(yīng)商設(shè)備封裝： *
包裝： *
2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FXMAR2104 Rev. 1.0.1
11
FXMAR2104
—
Dual-Supply,
4-Bit
Voltag
e
Translator
/
Isolator
/
for
Open
-Drain
and
Push-Pull
Applications
AC Characteristics
(17)
Output Load: CL = 50pF, RPU = NC, push-pull driver, and TA = -40°C to +85°C.
Symbol
Parameter
VCCB
Unit
4.5 to 5.5V
3.0 to 3.6V
2.3 to 2.7V
1.65 to 1.95V
Typ.
Max.
Typ.
Max.
Typ.
Max.
Typ.
Max.
VCCA = 4.5 to 5.5V
tPLH
A to B
1
3
1
3
1
3
1
3
ns
B to A
1
3
2
4
3
5
4
7
tPHL
A to B
2
4
3
5
4
6
7
ns
B to A
2
4
2
5
2
6
5
7
tPZL
OE to A
4
5
6
10
5
9
7
15
ns
OE to B
3
5
4
7
5
8
10
15
tPLZ
OE to A
65
100
65
105
65
105
65
105
ns
OE to B
5
9
6
10
7
12
9
16
tskew
A Port, B Port
(14)
0.5
1.5
0.5
1.0
0.5
1.0
0.5
1.0
ns
VCCA = 3.0 to 3.6V
tPLH
A to B
2.0
5.0
1.5
3.0
1.5
3.0
1.5
3.0
ns
B to A
1.5
3.0
1.5
4.0
2.0
6.0
3.0
9.0
tPHL
A to B
2.0
4.0
2.0
4.0
2.0
5.0
6.0
7.0
ns
B to A
2.0
4.0
2.0
4.0
2.0
5.0
3.0
5.0
tPZL
OE to A
4.0
8.0
5.0
9.0
6.0
11.0
7.0
15.0
ns
OE to B
4.0
8.0
6.0
9.0
8.0
11.0
10.0
14.0
tPLZ
OE to A
100
115
100
115
100
115
100
115
ns
OE to B
5
10
4
8
5
10
9
15
tskew
A Port, B Port
(14)
0.5
1.5
0.5
1.0
0.5
1.0
0.5
1.0
ns
VCCA = 2.3 to 2.7V
tPLH
A to B
2.5
5.0
2.5
5.0
2.0
4.0
1.0
3.0
ns
B to A
1.5
3.0
2.0
4.0
3.0
6.0
5.0
10.0
tPHL
A to B
2
5
2
5
2
5
6
ns
B to A
2
5
2
5
2
5
3
6
tPZL
OE to A
5.0
10.0
5.0
10.0
6.0
12.0
90.0
18.0
ns
OE to B
4.0
8.0
4.5
9.0
5.0
10.0
9.0
18.0
tPLZ
OE to A
100
115
100
115
100
115
100
115
ns
OE to B
65
110
65
110
65
115
12
25
tskew
A Port, B Port
(14)
0.5
1.5
0.5
1.0
0.5
1.0
0.5
1.0
ns
VCCA = 1.65 to 1.95V
tPLH
A to B
4.0
7.0
4.0
7.0
5.0
8.0
5.0
10.0
ns
B to A
1.0
2.0
1.0
2.0
1.5
3.0
5.0
10.0
tPHL
A to B
5
8
3
7
3
7
8
9
ns
B to A
4
8
3
7
3
7
3
7
tPZL
OE to A
11
15
11
14
28
14
23
ns
OE to B
6
14
6
14
6
14
9
19
tPLZ
OE to A
75
115
75
115
75
115
75
115
ns
OE to B
75
115
75
115
75
115
75
115
tskew
A Port, B Port
(14)
0.5
1.5
0.5
1.0
0.5
1.0
0.5
1.0
ns
Note:
14. Skew is the variation of propagation delay between output signals and applies only to output signals on the same
port (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 14). Skew is
guaranteed, but not tested.
15. AC Characteristic is guaranteed by Design and Characterization
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