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參數(shù)資料
| 型號： | FXMAR2102UMX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | TRANSLATOR 2BIT DUAL 8-UMLP |
| 標準包裝： | 5,000 |
| 邏輯功能： | 變換器，雙向，3 態(tài)，開路漏極 |
| 位數(shù)： | 2 |
| 輸入類型： | 電壓 |
| 輸出類型： | 電壓 |
| 數(shù)據(jù)速率： | * |
| 通道數(shù)： | 2 |
| 輸出/通道數(shù)目： | 1 |
| 差分 - 輸入:輸出： | 無/無 |
| 傳輸延遲（最大）： | 4ns |
| 電源電壓： | 1.65 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FXMAR2102 Rev. 1.0.1
5
FXMAR2102
—
Dual-Supply,
2-Bit
Volt
age
Translator
/
Isolator
for
I
2
C
Application
s
Functional Description
Power-Up / Power-Down Sequencing
FXM translators offer an advantage in that either VCC
may be powered up first. This benefit derives from the
chip design. When either VCC is at 0V, outputs are in a
high-impedance state. The control input (OE) is
designed to track the VCCA supply. A pull-down resistor
tying OE to GND should be used to ensure that bus
contention, excessive currents, or oscillations do not
occur during power-up/-down. The size of the pull-down
resistor is based upon the current-sinking capability of
the device driving the OE pin.
The recommended power-up sequence is:
1. Apply power to the first VCC.
2. Apply power to the second VCC.
3. Drive the OE input HIGH to enable the device.
The recommended power-down sequence is:
1. Drive OE input LOW to disable the device.
2. Remove power from either VCC.
3. Remove power from the other VCC.
Note:
4.
Alternatively, the OE pin can be hardwired to VCCA
to save GPIO pins. If OE is hardwired to VCCA,
either VCC can be powered up or down first.
Application Circuit
Figure 4. Application Circuit
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