參數(shù)資料
型號(hào): FX118DW
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁(yè)數(shù): 2/7頁(yè)
文件大?。?/td> 114K
代理商: FX118DW
2
Pin Number
Function
FX118DW
FX118P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Xtal:
Output of clock oscillator inverter.
No Internal Connection: It is recommended that, to improve noise conditions, this pin is connected to V
SS
.
LPF(1) Out:
The output of the Channel 1 Lowpass Filter. It is to be coupled to “B Mod(1) In” via a 1.0
μ
F
capacitor – see Figure 2.
B Mod(1) In:
The input to Channel 1 balanced modulator. Internally biased at V
DD
/2 it is to be coupled to
“LPF(1)” via a 1.0
μ
F capacitor – see Figure 2.
V
SS
:
Negative supply (GND).
C1 Out:
The analogue output of Channel 1.
C1 Amp Output:
Channel 1 amplifier with external components (see Figure 2) can be used to provide gain in
the signal path.
C1 In:
The negative input of Channel 1 Amplifier. Recommended external components are shown in Figure 2.
C2 In:
The negative input of Channel 2 Amplifier. Recommended external components are shown in Figure 2.
C2 Amp Output:
Channel 2 amplifier with external components (see Figure 2) can be used to provide gain in
the signal path.
C2 Out:
The analogue output of Channel 2.
V
:
The internal analogue bias line at V
DD
/2. It should be decoupled to V
SS
via a 1.0
μ
F or greater capacitor.
See Figure 2.
B Mod(2) In:
The input to Channel 2 balanced modulator. Internally biased at V
DD
/2 it is to be coupled to
“LPF(2)” via a 1.0
μ
F capacitor – see Figure 2.
LPF(2) Out:
The output of the Channel 2 Lowpass Filter. It is to be coupled to “B Mod(2) In” via a 1.0
μ
F
capacitor – see Figure 2.
V
:
The positive supply rail. A single positive supply voltage (3.0v – 5.0v) is required. Levels and voltages
within the Duplex Frequency Inverter are dependent upon this supply.
Xtal/Clock:
4.433619 MHz Xtal or externally derived clock is injected at this pin. See Figure 2. Operation of
the FX118 without a Xtal or clock input may cause device damage.
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