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參數資料
| 型號： | FX029D5 |
| 廠商： | CML MICROSYSTEMS PLC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 2 CHANNEL, AUDIO AMPLIFIER, PDSO24 |
| 封裝： | PLASTIC, SSOP-24 |
| 文件頁數： | 3/7頁 |
| 文件大?。?/td> | 470K |
| 代理商： | FX029D5 |
3
Application Information
External Components
Fig.2 Recommended External Components
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SERIAL CLOCK
IN 1A
IN 1B
IN 2A
IN 2B
IN 1C
OUT 2
OUT 1B
OUT 1A
OUT 3
IN 3
V
BIAS
V
SS
V
SS
V
SS
V
DD
V
DD
C
1
C
2
C
3
C
4
C
5
C
7
SERIAL DATA
LOAD/LATCH
FX029
DW/J
SERIAL
CLOCK
SERIAL
DATA
t
PWL
PWH
DS
t
LLW
t
LLD
t LLO
DH
LOAD/LATCH
D0
1ST
CLOCK
PULSE
14TH
CLOCK
PULSE
D13
D12
D1
Serial Interface Timing
Component Recommendations
Component
Value
C
1
0.1
F
C
2
0.1
F
C
3
0.1
F
C
4
0.1
F
C
5
0.1
F
C
6
Not Used
C
7
1.0
F
Tolerances 20%
Input capacitors C
1 to C5 are only required for ac
input signals; dc input signals do not require these
components.
The gain of the uncommitted stage (3) is set by
external components employed around the input and
output pins (see Specification page).
Application Recommendations
To avoid noise and instability the following practices
are recommended:
(a) Use a clean, well-regulated power supply.
(b) Keep tracks short.
(c) Inputs and outputs should be shielded wherever
possible.
(d) Analogue tracks should not run parallel to digital
tracks.
(e) A “Ground Plane” connected to V
SSwill assist in
eliminating external pick-up on the channel input
and output pins.
(f) Avoid running high level outputs adjacent to low
level inputs.
(g) The serial clock should not be running
consecutively when not in the process of actually
loading data.
Fig.3 Serial Timing Diagram - see Specification page for timing specifications
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