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參數(shù)資料
| 型號(hào)： | FX019DW |
| 廠商： | CML MICROSYSTEMS PLC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, PDSO16 |
| 封裝： | PLASTIC, SOIC-16 |
| 文件頁(yè)數(shù)： | 4/7頁(yè) |
| 文件大?。?/td> | 102K |
| 代理商： | FX019DW |
4
Table 2 Gain Control Word Format
Bit 3
Bit2
Bit 1
Bit 0
Stage 1, 2, 3
Stage 4
MSB
LSB
(0.43dB)
(2.0dB)
0000
OFF
0001
-3.0
-14.0dB
0010
-2.571
-12.0
0011
-2.143
-10.0
0100
-1.714
-8.0
0101
-1.286
-6.0
0110
-0.857
-4.0
0111
-0.428
-2.0
1000
0
1001
0.428
2.0
1010
0.857
4.0
1011
1.286
6.0
1100
1.714
8.0
1101
2.143
10.0
1110
2.571
12.0
1111
3.0
14.0
t
LLW
Load/Latch Pulse Width
t
LLO
Load/Latch Over Time
t
DS
Data Set-up Time
t
DH
Data Hold Time
t
LLD
Load/Latch Delay
Timing
t
PWH
Serial Clock "High" Pulse Width
t
PWL
Serial Clock "Low" Pulse Width
The gain of each amplifier block (Channel 1 to
Channel 4) in the FX019 is set by a separate 8-bit
data word ( bit 7 to bit 0 ). This 8-bit word, consisting
of 4 Address bits (bit 7 to bit 4) and 4 Gain Control
bits (bit 3 to bit 0), is loaded to the Control Data Input
in serial format using the external data clock.
Data Loading
The 8-bit data word is loaded
bit 7 first and bit 0 last.
Bit 7 must be a logic “1” to address the chip.
If bit 7 in the word is a logic “0” that 8-bit word will not be
executed. The Chip Select input permits the use of two
devices in a system; To facilitate this, Bit 6 can be either
a logic “0” or “1.” Figure 4 (below) shows the timing
information required to load and operate this device.
Control Data and Timing
Fig.4 Serial Control Data Loading Diagram
Chip
1
Chip
2
Table 1 Address Word Format
Bit 7 Bit 6
Bit 5
Bit 4
Channel
Chip
MSB
LSB
Selected
Select
Number
1000
1
0
1001
2
0
1010
3
0
1011
4
0
1100
1
1101
2
1
1110
3
1
1111
4
1
Data is loaded to the FX019 on the rising edge of the
Serial Clock. Loaded data is executed on the falling
(rising) edge of the Load/Latch (Load/Latch) pulse.
Table 1 shows the format of each 4-bit Address word,
Table 2 shows the format of each Gain Control word
with Figure 4 describing the data loading operation and
timing.
SERIAL DATA CLOCK
t
PWL
tPWH
tDS
Loaded Last
Logic ’1’
Loaded
First
BIT 7
BIT 6
BIT 1
BIT 0
t
DH
SERIAL DATA IN
(ONE 8-BIT WORD)
t LLO
8th
Clock
Pulse
Next
Clock
Pulse
t LLD
tLLW
LOAD/LATCH
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