參數(shù)資料
型號(hào)： FW803
英文描述： PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device
中文描述： PHY的IEEE 1394A端口三線收發(fā)器/仲裁器裝置
文件頁(yè)數(shù)： 21/24頁(yè)
文件大小： 395K
代理商： FW803
Agere Systems Inc.
21
Data Sheet, Rev. 3
June 2001
Three-Cable Transceiver/Arbiter Device
FW803 PHY
IEEE
1394A
Internal Register Configuration
(continued)
The meaning of the register fields with the port status page are defined by Table 11 below.
Table 11. PHY Register Port Status Page Fields
Field
Size Type
Power Reset
Value
Description
AStat
2
r
—
TPA line state for the port:
00
2
= invalid
01
2
= 1
10
2
= 0
11
2
= Z
TPB line state for the port (same encoding as AStat).
If equal to one, the port is a child; otherwise, a parent. The
meaning of this bit is undefined from the time a bus reset is
detected until the PHY transitions to state T1: Child Hand-
shake during the tree identify process (see Section 4.4.2.2 in
IEEE
Standard 1394-1995).
If equal to one, the port is connected.
If equal to one, incoming TPBIAS is detected.
If equal to one, the port is disabled.
Indicates the maximum speed negotiated between this PHY
port and its immediately connected port; the encoding is the
same as for they PHY register Max_speed field.
Enable port event interrupts. When set to one, the PHY will
set Port_event to one if any of connected, bias, disabled, or
fault (for this port) change state.
Set to one if an error is detected during a suspend or resume
operation. A write of one to this bit clears it to zero.
BStat
Child
2
1
r
r
—
0
Connected
Bias
Disabled
Negotiated_speed
1
1
1
3
r
r
0
0
0
rw
r
000
Int_enable
1
rw
0
Fault
1
rw
0
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