- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370260 > FW80200M600 Microprocessor PDF資料下載
參數(shù)資料
| 型號： | FW80200M600 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 13/36頁 |
| 文件大?。?/td> | 461K |
| 代理商： | FW80200M600 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
Intel
80200 Processor based on Intel
XScale
Microarchitecture
Package Information
Datasheet
August 2002
13
3.0
Package Information
3.1
Package Introduction
The Intel
80200 processor is offered in a Plastic Ball Grid Array (PBGA) package. See
Figure 2
“241-Lead PBGA Package” on page 17
.
3.1.1
Functional Signal Definitions
This section defines the pins and signals in the following tables:
Table 2 “Pin Description Nomenclature” on page 13
Table 3 “Power Pins” on page 14
Table 4 “Signal Pin Description” on page 14
Table 5 “JTAG Pins” on page 16
3.1.1.1
Signal Pin Descriptions
Table 2.
Pin Description Nomenclature
Symbol
Description
I
Input pin only
Output pin only
Pin can be either an input or output
Pin must be connected as described
NO CONNECT. Do not make electrical connections to these balls.
While the
RESETOUT#
pin is asserted, the pin:
Rst(1) Is driven to Vcc
Rst(0) Is driven to Vss
Rst(X) Is driven to unspecified state (1 or 0, buses may contain a mix of 1 and 0 signals)
Rst(H) Is pulled up to Vcc
Rst(L) Is pulled down to Vss
Rst(Z) Floats
Rst(Q) Is a valid output
Since RESET# is asynchronous, these are asynchronous events.
While the Intel
80200 processor is in HOLD mode (
HOLD
asserted and took effect), the pin:
Hld(Z) Floats
Hld(Q) is a valid output
Hld(1) is driven to Vcc
Note: When both
HLDA
and
RESETOUT#
are asserted, then HOLD mode takes priority; the
output pins assume the state specified by Hld(...). The
HOLD
pin is also honored during Idle
and Sleep modes; the output pins assume the state specified by Hld(...).
While the Intel
80200 processor is in Idle or Sleep mode (software selected), pin:
Slp(1) Is driven to Vcc
Slp(0) Is driven to Vss
Slp(X) Is driven to unspecified state
Slp(Q) Is a valid output
O
I/O
-
N/C
Rst(...)
Hld(...)
Slp(...)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FW80200M733 | Microprocessor |
| FW802 | Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device |
| FW802A | Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device |
| FW802A-DB | Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device |
| FW802C | FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW80200M600 S L677 | 制造商:Intel 功能描述:MPU 80200 Processor 32-Bit 0.18um 600MHz 241-Pin BGA |
| FW80200M600 SL677 | 制造商:Intel 功能描述: |
| FW80200M600SL677 | 功能描述:IC I/O PROCESSOR 600MHZ 241-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| FW80200M733 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| FW80200M733 S L678 | 制造商:Intel 功能描述:MPU 80200 Processor 32-Bit 0.18um 733MHz 241-Pin BGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。